User manual

Hardware Description
15
Additionally, the following measures can reduce power consumption considerably:
• switching off the TFT supply voltage
• putting peripheral chips like Ethernet controller and / or PHY or serial driver devices
in power down mode
• putting the SDRAM into self-refresh mode
5.11. Timer Counter (TC)
The StampA5D3x features two blocks of timer counters with three counters each. The
second block is not present on all variations of the StampA5D3x series. Compare Table2.1,
“SAMA5D3X Device Differences”.
The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded
to form a 32-bit or 48-bit timer/counter. The timers can run on the internal clock sources
MCK/2, MCK/8, MCK/32, MCK/128, SLCK or the output of another timer channel. External
clocks may be used as well as the counters can generate signals on timer events. They
also can be used to generate PWM signals.
5.12. Pulse Width Modulation Controller (PWM)
The PWM controls four channels independently. Each Channel controls two
complementary square output waveforms. Characteristics of the output waveforms such
as period, duty-cycle, polarity and dead-times are configured through the user interface.
Each channel selects and uses one of the clocks provided by the clock generator. The clock
generator provides several clocks resulting from the division of the PWM master clock
(MCK).
• 4 Independent Channels
• Common clock Generator Providing Thirteen Different Clocks
• 2 2-bit Gray Up/Down Channels for Stepper Motor Control
• Synchronous Channel Mode
• 2 Independent Event Lines to Synchronize ADC Conversions
• Comparision Units
• Write Protected Registers
5.13. Periodic Interval Timer (PIT)
The PIT consists of a 20-bit counter running on MCK / 16. This counter can be preloaded
with any value between 1 and 2
20
. The counter increments until the preloaded value is
reached. At this stage it rolls over and generates an interrupt. An additional 12-bit counter
counts the interrupts of the 20 bit counter.