User manual

Hardware Description
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Hardware Handshaking. The hardware handshaking feature enables an out-of-band
flow control by automatic management of the pins RTS and CTS. The receive DMA channel
must be active for this mode. The RTS signal is driven high if the receiver is disabled or if
the DMA indicates a buffer full condition. As the RTS signal is connected to the CTS line of
the connected device, its transmitter is thus prevented from sending any more characters.
ISO7816. The USARTs have an ISO7816-compatible mode which permits interfacing
with smart cards and Security Access Modules (SAM). Both T=0 and T=1 protocols of the
ISO7816 specification are supported.
IrDA. The USART features an infrared (IrDA) mode supplying half-duplex point-to-
point wireless communication. It includes the modulator and demodulator which allows
a glueless connection to the infrared transceivers. The modulator and demodulator are
compliant with the IrDA specification version 1.1 and support data transfer speeds ranging
from 2.4 kb/s to 115.2 kb/s.
Signals of the Serial Interfaces. All UARTs/USARTs have one receiver and one
transmitter data line (full duplex). Not all USARTs are implemented with full modem
control lines. Furthermore the available lines depend largely on the used multiplexing.
Most modem control lines can be implemented with standard digital ports.
Hardware Interrupts. There are several interrupt sources for each USART:
• Receive: RX Ready, (DMA) Buffer Full, End of Receive Buffer
• Transmit: TX Ready, (DMA) Buffer Empty, End of Transmit Buffer, Shift Register Empty
• Errors: overrun, parity, framing, and timeout errors
• Handshake: the status of CTS has changed
• Break: the receiver has detected a break condition on RXD
• NACK: non acknowledge (ISO7816 mode only)
• Iteration: the maximum number of repetitions has been reached (ISO7816 mode only)
Please refer to the chapter about the DMA unit (PDC) for a description of the "Buffer Full"
and "End of Receive / Transmit Buffer" events.
5.28. Synchronous Peripheral Interface (SPI)
The StampA5D3x features two SPI ports, with four respectively one chipselect available.
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that
provides communication with external devices in Master or Slave Mode. It also enables
communication between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data
bits to other SPIs. During a data transfer, one SPI system acts as the "master" which
controls the data flow, while the other devices act as "slaves" which have data shifted into
and out by the master.