User manual
Hardware Description
24
In grayscale mode, the input data stream is stored in memory without any processing. The
12-bit data, which represent the grayscale level for the pixel, is stored in memory one or
two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec
datapath is not available when grayscale image is selected.
5.31. LCD controller
The LCD controller supports single scan active TFT LCD modules with a resolution of up
to 2048x2048 with a color depth of up 24 bits per pixel. As the video memory is shared, a
maximum resolution of 1280x720 pixels is recommended to maintain a reasonable memory
bandwidth for other applications.
The LCD controller relies on a relatively simple frame buffer concept, which means that
all graphics and character functions have to be implemented in software: character sets
and graphic primitives are not integrated in the controller.
5.31.1. LCDC Initialisation and LCD Power Sequencing
LCD cells (pixels) should not be subjected to DC power for prolonged periods of time,
as chemical decomposition might take place. The LCD controller therefore provides for
a strict AC control of the LCD pixels. To do so, the LCD controller has to be initialized
appropriately. Switching on the LCD supply voltage therefore has to take place after the
LCDC initialization or shortly before.
Accordingly, the LCDC should not be powered down without deactivating the LCD supply
voltage. The same is true if the LCDC is stopped indirectly by stopping the respective
clock source, namely the PLLA.
The LCD backlight supply is not involved in these considerations. It may switched on or
off at any time independently of the state of the LCDC.
5.31.2. LCDC Frame Buffer
The LCDC Frame Buffer typically resides in the external RAM.
The LCDC video memory is organized as a frame buffer in a straight forward way. It
supports color depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a
packed form with no unused bits in the video memory.
The color resolutions of 1, 2, 4, and 8 bpp (bits per pixel) use a palette table which is made
up of 16-bit entries. The value of each pixel in the frame buffer serves as an index into
the palette table. The value of the respective palette table entry is output to the display
by the LCDC, see Table5.6, “LCDC palette entry”.
Bit[14..10] Bit[9..5] Bit[4..0]
Blue[7..3] Green[7..3] Red[7..3]
Table5.6.LCDC palette entry
The bits 2..0 of each color channel are not used in the palettized configuration — they
are set to 0.