User manual

Layout Description

Pin Assignment Processor Pin

1 AI0 PD24/AD4

2 AI1 PD25/AD5

3 AI2 PD26/AD6

4 AI3 PD27/AD7

5 AI4 PD28/AD8

6 AI5 PD29/AD9

7 AI6 PD30/AD10/PCK0

8 AI7 PD31/AD11/PCK1

9 GND GND

Table4.8.X19 Pin Assignment

4.1.14. X20 Three-way Pin Header for FTDI USB Debug Console

These three pins export the DBGU of the StampA5D36 in LVTTL-level. They are for

connection with the FTDI USB/TTL converter cable TTL-232R-RPi.

4.1.15. X21 IF Ten-way Pin Header

Pin-header X21 has ten contacts in 2.54 mm grid pitch. It contains the necessary USART

LVTTL Signals to connect a gpio.net card. Besides that X21 can be used customer specific.

Pin Processor Pin

1 PC29/URXD0/PWMFI2/ISI_D8

2 PC30/UTXD0/ISI_PCK

3 PE18/A18/RXD3

4 PE19/A19/TXD3

5 PA30/TWD0/URXD1/ISI_VSYNC

6 PA31/TWCK0/UTXD1/ISI_HSYNC

7 PE16/A16/CTS3

8 PE17/A17/RTS3

9 3V3

10 GND

Table4.9.X21 Pin Assignment

4.1.16. X22 Extension Bar

Pin-header X22 has 50 contacts in 2.1 mm grid pitch. It exports a variety of pins for free

use.

Pin GPIO Periph. A Periph. B Periph. C  Periph. C Periph. B Periph. A GPIO Pin

1 VCC3.3  GND 2

3 PD24 AD4      AD5 PD25 4

5 PD26 AD6      AD7 PD27 6

7 PD28 AD8      AD9 PD29 8