User manual

Layout Description
11
Pin GPIO Periph. A Periph. B Periph. C  Periph. C Periph. B Periph. A GPIO Pin
9 PD30 AD10 PCK0    PCK1 AD11 PD31 10
11 VCC5  GND 12
13 PC22 SPI1
MISO
     SPI1
MOSI
PC23 14
15 PC24 SPI1
SPCK
     SPI1
NPCS0
PC25 16
17 PB0 GTX0 PWM H0    PWM L0 GTX1 PB1 18
19 PB2 GTX2 TK1   GND 20
21 PB3 GTX3 TF1    PWM H1 GRX0 PB4 22
23 PB5 GRX1 PWM L1    TD1 GRX2 PB6 24
25 PB7 GRX3 RK1    PWM H2 GTXCK PB8 26
27 PB9 GTXEN PWM L2    RF1 GTXER PB10 28
29 PB11 GRXCK RD1   GND 30
31 PB12 GRXDV PWM H3    PWM L3 GRXER PB13 32
33 PB14 GCRS CANRX1    CANTX1 GCOL PB15 34
35 PB16 GMDC      GMDIO PB17 36
37 PC31 FIQ PWMFI1    PWM L1 IRQ PE31 38
39 PE28 NCS2 TIOB2 LCD
DAT23
 GND 40
41 PD0 MCI0 CDA      MCI0 DA0 PD1 42
43 PD2 MCI0 DA1      MCI0 DA2 PD3 44
45 PD4 MCI0 DA3    PWM L2 TIOB0 MCI0 DA5 PD6 46
47 PD7 MCI0 DA6 TCLK0 PWM H3  PWM L3  MCI0 DA7 PD8 48
49 PD9 MCI0 CK    GND 50
Table4.10.Pin Assignment X22
4.1.17. X23/X29 Nine-way Digital Out Pin Header
Pin-header X23/X29 has nine contacts in 3.5 mm grid pitch. X23 and X29 are identically
assigned. The Pins are connected to a 5V/12V/24V level shifter. Refer to the schematics
AppendixF, PanelA5 Schematics for details.
Pin Assignment Processor Pin
1 DO0 PB0/GTX0/PWMH0
2 DO1 PB1/GTX1/PWML0
3 DO2 PB2/GTX2/TK1
4 DO3 PB3/GTX3/TF1
5 DO4 PB4/GRX0/PWMH1
6 DO5 PB5/GRX1/PWML1
7 DO6 PB6/GRX2/TD1
8 DO7 PB7/GRX3/RK1
9 GND GND
Table4.11.X11 Pin Assignment