StampA5D3x/PortuxA5D3x Technical Reference
StampA5D3x/PortuxA5D3x StampA5D3x/PortuxA5D3x: Technical Reference Copyright © 2014 taskit GmbH All rights to this documentation and to the product(s) described herein are reserved by taskit GmbH. This document was written with care, but errors cannot be excluded. Neither the company named above nor the seller assumes legal liability for mistakes, resulting operational errors or the consequences thereof. Trademarks, company names and product names may be protected by law.
StampA5D3x/PortuxA5D3x Table of Contents 1. Introduction ................................................................................................................. 1 2. Scope ........................................................................................................................... 2 3. Overview of Technical Characteristics ........................................................................ 3 3.1. CPU ..............................................................................
StampA5D3x/PortuxA5D3x 5.19. Two-wire Interface (TWI) .............................................................................. 5.20. Multimedia Card Interface (MCI) ................................................................. 5.21. USB Host Port (UHP) .................................................................................... 5.22. USB Device Port (UDP) ................................................................................. 5.23. Ethernet MAC (EMAC) ............................
StampA5D3x/PortuxA5D3x List of Figures H.1. StampA5D3x Dimensions ....................................................................................... I.1. PortuxA5 FX8,BT ..................................................................................................... I.2. PortuxA5 VG96,TFT ................................................................................................ I.3. PortuxA5 Interface ..........................................................................................
StampA5D3x/PortuxA5D3x List of Tables 2.1. SAMA5D3X Device Differences ................................................................................ 2 5.1. Bus Matrix Masters ................................................................................................ 10 5.2. Bus Matrix Slaves .................................................................................................. 10 5.3. AT91SAMA5D3x Clocks ...................................................................................
Introduction 1. Introduction The StampA5D3x is intended to be used as a small size "intelligent" CPU module as well as a universal Linux CPU card. It can be used anywhere where restricted energy and space requirements play a role. The design of the StampA5D3x is limited to the processors core needs like DDRAM and Flash, thus giving the customer a wide-ranged choice of configurations of the peripherals and environment.
Scope 2. Scope This document describes the most important hardware features of the StampA5D3x. It includes all informations necessary to develop a customer specific hardware for the StampA5D3x. The Operating System Linux is described in a further document. The AT91SAMA5D3x processor series consists of several MPUs, like the SAMA5D31, SAMA5D35 and SAMA5D36. Not all processors will be implemented as a Stamp CPU module, but these processors only vary in their variety of peripherals.
Overview of Technical Characteristics 3. Overview of Technical Characteristics 3.1. CPU Atmel AT91SAMA5D3x Embedded Processor featuring an Cortex-A5™ ARM® core with ARM v7-A Thumb2® instruction set. • CPU Frequency 528 MHz • 32KB Instruction Cache • 32KB Data Cache • Memory Management Unit (MMU) • Floating Point Unit (VFPv4) • 3.3V Supply Voltage, 1.8V Memory Bus Voltage, 1.25V Core Voltage 3.2.
Overview of Technical Characteristics 2 • 3x Two Wire Interface (TWI, I C) • High Speed MultiMedia Card Interface • 2x CAN Controller • Soft Modem • 4x PWM • Touch Screen Analog-to-Digital Converter ADC • LCD/TFT Controller (2048 x 2048 pixels) • JTAG Debug Port • Digital Ports - up to 150 available • Control Signals: IRQs, BMS, SHDN, WKUP • 3x Programmable Clocks • Image Sensor Interface Some of the various functions are realized by multiplexing connector pins; therefore not all functions may be used at t
Overview of Technical Characteristics 3.6. Miscellaneous • 2x Three-channel 32-Bit Timer/Counter • RTC Battery Backed • Periodic Interval Timer (PIT) • Watchdog Timer (WDT) • Temperature Sensor 3.7. Power Supply • 3.3V Power Supply • 3V Backup Power Supply, e.g. from a Lithium Battery 3.8. Dimensions • Dimensions: 53.
Security Characteristics 4. Security Characteristics 4.1. Atmel® Secure Boot Solution The SAMA5D3 Microcontrollers can be configured to run in standard boot mode or a secure boot mode. In secure boot mode the Microcontroller only boots an image with a correct cryptographic checksum. Information on how the secure boot mode can be enabled, and how the chip operates in this mode is provided by Atmel ® only under a NDA. Please contact the taskit support on how to obtain this. 4.2.
Security Characteristics 4.4. True Random Number Generator (TRNG) The True Random Generator (TRNG) passes the American NIST Special Publication 800-22 and the Diehard Random Tests Suites. It provides a 32-bit value every 84 clock cycles. 4.5. taskit Vaultsec In the Stamp series taskit has implemented a further cryptographic chip, that supports secure, unreadable storing of keys for SHA-256 hashes and ECC public/private key cryptographic algorithms.
Hardware Description 5. Hardware Description 5.1. Mechanics The StampA5D3x series was designed as a flexible CPU-Module, which can be connected to base boards via 2x 100-pin fine pitch low profile Hirose ® FX8 connectors. The size of the StampA5D3x's PCB is only 53.6x42x6.0 mm fitting it in even the smallest design. While having implemented the sensible CPU, DDRAM and Flash design it still exports almost all possible CPU-Pins on it's connectors to allow a flexible design on base boards.
Hardware Description 5.3.1. NAND Flash The StampA5D3x is equipped with a 256 MB NAND flash with 100000 erase and write cycles. Customer specific adaptations are possible up to 1 GB on-board NAND flash. It is connected to chip select three (NCS3) of the microcontroller. NAND flash has a different organisation of transistors than the commonly used NOR flash. While it allows a much higher density and thus an increase in storage capacity, there are some differences which need to be kept in mind.
Hardware Description state machine in the chip, which allows to accept new instructions, before the previous one has finished executing. 5.3.4. SRAM The StampA5D3x is equipped with 128 KB internal SRAM. The internal SRAM can be accessed in one bus cycle and may be used for time critical sections of code or interrupt handlers. 5.4. Bus Matrix The bus matrix of AT91SAM-controllers allows many master and slave devices to be connected independently of each other.
Hardware Description Slave 7 DDR2 Port 0 Slave 8 DDR2 Port 1 Slave 9 DDR2 Port 2 Slave 10 DDR2 Port 3 Slave 11 Peripheral Bridge 0 Slave 12 Peripheral Bridge 1 Table 5.2. Bus Matrix Slaves 5.5.
Hardware Description 5.7. Reset Controller (RSTC) The embedded microcontroller has an integrated Reset Controller which samples the backup and the core voltage. The presence of a backup voltage (VDDBU) when the card is powered down speeds up the boot time of the microcontroller. 5.8. Peripheral Input/Output Controller (PIO) The StampA5D3x has a maximum of 150 freely programmable digital I/O ports on its connectors. These pins are also used by other peripheral devices.
Hardware Description 5.9. Clock Generation 5.9.1. Processor Clocks The AT91SAMA5D3x has no PLLB, but provides the 480 MHz USB Clock via a UPLL. The CPU generates its clock signals based on two crystal oscillators: One slow clock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 18.432 MHz. The slow clock oscillator also serves as the time base for the real time timer.
Hardware Description • SMD Clock • USB Host Clock (common for all three channels) • USB Device Clock • Programmable Clocks The PMC status register provides "Clock Ready" or, respectively, "PLL Lock" status bits for each of these clocks. An interrupt is generated when any of these bits changes from 0 to 1. The PMC provides status flags for the • Main Oscillator • Master Clock • PLLA • PLLB • Programmable Clocks The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency register.
Hardware Description Additionally, the following measures can reduce power consumption considerably: • switching off the TFT supply voltage • putting peripheral chips like Ethernet controller and / or PHY or serial driver devices in power down mode • putting the SDRAM into self-refresh mode 5.11. Timer Counter (TC) The StampA5D3x features two blocks of timer counters with three counters each. The second block is not present on all variations of the StampA5D3x series. Compare Table 2.
Hardware Description The PIT is intended for use as the operating system’s scheduler interrupt. 5.14. Watchdog Timer The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128). The maximum watchdog timeout period is therefore equal to 16 seconds. If enabled, the watchdog timer asserts a hardware reset at the end of the timeout period. The application program must always reset the watchdog timer before the timeout is reached.
Hardware Description Instance T/R Channel Interface Number USART1 Receive 6 TWI0 Transmit 7 TWI0 Receive 8 TWI1 Transmit 9 TWI1 Receive 10 UART0 Transmit 11 UART0 Receive 12 SSC0 Transmit 13 SSC0 Receive 14 SMD Transmit 15 SMD Receive 16 Table 5.4. DMAC0 Channels Definition DMAC1 handles transfers between peripherals and memory from peripherals connected on APB1 ( AMBA Peripheral Bridge 1).
Hardware Description which improves microcontroller performance. The DMAC supports single transfer and chained buffer transfer. In chained buffer transfer mode, the address is automatically incremented, when the countable limit of the current transfer buffer is reached. To launch a transfer, the peripheral triggers its associated DMA channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
Hardware Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
Hardware Description The USB device port can also be implemented to power on the board. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pullup. 5.23.
Hardware Description The StampA5D3x integrates two CAN controllers, CAN0 and CAN1. The CAN controller is not present on all variations of the StampA5D3x series. Compare Table 2.1, “SAMA5D3X Device Differences”. 5.26. Software Modem Device (SMD) The SMD is a block for communication via a modem's Digital Isolation Barrier (DIB) with a complementary Line Side Device (LSD). Power and clock are supplied by the SMD and consumed by the LSD. The data flow is bidirectional.
Hardware Description Hardware Handshaking. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The receive DMA channel must be active for this mode. The RTS signal is driven high if the receiver is disabled or if the DMA indicates a buffer full condition. As the RTS signal is connected to the CTS line of the connected device, its transmitter is thus prevented from sending any more characters. ISO7816.
Hardware Description A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Hardware Description In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not available when grayscale image is selected. 5.31. LCD controller The LCD controller supports single scan active TFT LCD modules with a resolution of up to 2048x2048 with a color depth of up 24 bits per pixel.
Hardware Description The same scheme as above is used in the 16-bit color resolution configuration, although in this case the frame buffer entry is output directly to the display instead of indexing a palette table. In the 24-bit color resolution configuration, each frame buffer entry consists of one byte for each color, see Table 5.7, “LCDC 24 bit memory organization”. Bit[23..16] Bit[15..8] Bit[7..0] Blue[7..0] Green[7..0] Red[7..0] Table 5.7.
Design Considerations 6. Design Considerations 6.1. Ethernet Controller (EMAC) The emac needs an aditional PHY design. The emac supports both, MII and RMII interface. Please take care of the specific layout requirements of the Ethernet port when designing a base board. The two signals of the transmitter pair (ETX+ and ETX-) should be routed in parallel (constant distance, e.g. 0.5mm) with no vias on their way to the RJ45-jack. The same is true for the receiver pair (ERX+ and ERX-).
Design Considerations USB High-Speed. If designing USB High-Speed a wave impedance of 90 Ω on the traces should be respected. The traces shoud be routed as short as possible and in parallel with as low parallel capacitance as possible. 6.3. USB Device Controller (UDP) External Parts. A few external parts are required for the proper operation of the UDP: • No pull-down resistors are needed. • No series resistors are needed.
Design Considerations described in this chapter, or in secure boot mode. How the secure boot mode can be enabled and how the chip operates in this mode is provided in an application by Atmel®, which is only available under NDA. Please contact taskit support, if you want to employ the secure bootloader. The ROM code first samples the BMS signal, if it is low, it will boot from NOR flash connected to NCS0 of the external bus. If it is high it tries to retrieve valid code from external memories.
Design Considerations Boot Value SPI0 NPCS0 SD Card SD Card NAND MCI0 MCI1 Flash SPI0 NPCS1 TWI EEPROM SAM-BA 0 Yes Yes Yes Yes Yes Yes Yes 1 Yes No Yes Yes Yes Yes Yes 2 Yes No No Yes Yes Yes Yes 3 Yes No No No Yes Yes Yes 4 Yes No No No Yes Yes Yes 5-7 No No No No No No Yes Table 6.1. SAMA5D3X Boot Sequence Please note, that boot from SD Card (MCI1) is not working according to the errata of the Microcontroller. 6.4.2.
Design Considerations Boot Device TWI EEPROM TWI0 DBGU Pin Pio Line Pin on Stamp NPCS1 PD14 IO 91 TWD0 PA30 IO 38 TWCK0 PA31 IO 37 DRXD PB30 Bus 43 DTXD PB31 Bus 42 Table 6.2.
Peripheral Color Codes Appendix A. Peripheral Color Codes This table matches the color used to identify various peripherals in tables.
Peripheral Identifiers Appendix B.
Peripheral Identifiers ID Mnemonic Peripheral Name 39 SSC1 Synchronous Serial Controller 1 40 CAN0 Can Controller 0 41 CAN1 Can Controller 1 42 SHA Secure Hash Algorithm 43 AES Advanced Encryption Standard 44 TDES Triple Data Encryption Standard 45 TRNG True Random Generator 46 ARM Performance Monitor Unit 47 AIC Advanced Interrupt Controller 48 FUSE Fuse Controller 49 MPDDRC MPDDR Controller 50-63 Reserved Table B.1.
Address Map (Physical Address Space) Appendix C. Address Map (Physical Address Space) After the execution of the remap command the 4 GB physical address space is separated as shown in the following table. Accessing these addresses directly is only possible if the MMU (memory management unit) is deactivated. As soon as the MMU is activated the visible address space is changed completely.
Address Map (Physical Address Space) Address (Hex) Mnemonic Function F003 8000 SFR Special Functions Register F800 0000 HSMCI1 High Speed Multimedia Card / SD-Card Interface 1 F800 4000 HSMCI2 High Speed Multimedia Card / SD-Card Interface 2 F800 8000 SPI1 Serial Peripheral Interface 1 F800 C000 SSC1 Serial Synchronous Controller 1(I S) F801 0000 CAN1 CAN Interface 1 F801 4000 TC3, TC4, TC5 3 Timer Counter, 16-Bit F801 8000 TSADC Touch Controller ADC Interface F801 C000 TWI2 Two
StampA5D3X Pin Assignment Appendix D. StampA5D3X Pin Assignment Pin GPIO Periph. A Periph. B Periph. C Periph. C Periph. B Periph.
StampA5D3X Pin Assignment Pin GPIO Periph. A Periph. B Periph. C 77 Periph. C Periph. B Periph. A GND GPIO VBATT Pin 78 79 BMS NRST 80 81 WKUP SHDN 82 DIBP 84 DIBN 86 83 85 GND HHSDPC 87 HHSDMC TCK 88 TDO 90 HHSDPB TMS 92 93 HHSDMB TDI 94 JTAGSEL 96 89 91 GND 95 97 GND HHSDPA DHSDP NTRST 98 99 HHSDMA DHSDM GND 100 Table D.1. Pin Assignment BUS Interface X2 Pin GPIO Periph. A Periph. B Periph. C 1 Periph. C Periph. B Periph.
StampA5D3X Pin Assignment Pin GPIO Periph. A Periph. B Periph. C 43 PA25 LCD DISP 45 PA23 LCD DAT23 47 PWM L1 ISI D7 GND Periph. C Periph. B Periph.
StampA5D3x Electrical Characteristics Appendix E. StampA5D3x Electrical Characteristics Ambient temperature 25℃, unless otherwise indicated Symbol Description Parameter Min. Typ. Max Unit VCC Operating Voltage 3.0 3.3 3.6 V VMEM Memory Bus Voltage 1.7 1.8 1.95 V VRES Reset Treshhold TRES Duration Pulse VIH of 2.93 Reset 100 High-Level Voltage Input 3.3V 2.0 VCC + 0.3 V VIL Low-Level Voltage Input 3.3V -0.3 0.
StampA5D3x Clock Characteristics Appendix F. StampA5D3x Clock Characteristics Symbol Description Dependency MAINCK Main Oscillator Frequency 12.000 MHz SLCK Slow Clock 32.768 KHz PLLACK PLLA Clock MAINCK 528.000 MHz PCK Processor Clock PLLACK 528.000 MHz MCK Master Clock PCK 132.000 MHz DDRCK DDRAM Clock MCK 132.000 MHz BCK Baudrate Clock MCK 1.5% 10.37(max) MHz UTMI PLL USB Clock MAINCK 0.25% 480.000 Table F.1.
StampA5D3x Environmental Ratings Appendix G. StampA5D3x Environmental Ratings Symbol TA Description Parameter Ambient temperature Relative Humidity no condensation Operating Storage Min. Max. Min. Max. -30 85 -45 85 ℃ 90 %RH 90 Absolute Humidity <= Humidity@TA = 60℃, 90%RH Corrosive Gas not admissible Table G.1.
StampA5D3x Dimensions Appendix H. StampA5D3x Dimensions Figure H.1.
X11 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PC22/SPI1_MISO PC23/SPI1_MOSI PC24/SPI1_SPCK PC25/SPI1_NPCS0 PC26/SPI1_NPCS1/TWD1/ISI_D11 PC27/SPI1_NPCS2/TWCK1/ISI_D10 PC28/SPI1_NPCS3/PWMFI0/ISI_D9 PC29/URXD0/PWMFI2/ISI_D8 PC30/UTXD0//ISI_PCK PC31/FIQ/PWMFI1 PC
TFT XF2M-5015-1 X4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 39r 39r 0r 0r 0r 0r 0r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r 39r R82 R83 R84 R85 R86 R87 R88 R89 R76 R77 R80 R81 R75 R26 R70 R71 R72 R73 R74 R56 R57 R58 R59 R61 R69 R45 R46 R47 R53 R54 R55 R30 R31 R32 R33 R35 R36 R37 R38 +5V-EXT PA17/LCDDAT17//ISI
LED Reset BMS NRST PE27/NCS1/TIOA2/LCDDAT22 IC27-D LED3 LED2 LED BLUE 5 6 4 e 74LVC86 74LVC86 R25 330r SP1 PS1240P02CT3 TDK IC27-B LED GREEN 2 3 1 e IC27-A 74LVC86 9 8 10 e IC27-C 74LVC86 R97 LED RED 100r R101 R99 100r 100r R24 330r X6 LED1 100r R98 100r R96 100r 13 11 12 e +3V3 DNP J12 LED_BLUE X10 150r R29 PE14/A14 1 2 330r R2 PE13/A13 1 2 3 R100 470r R1 PB30/DRXD PB31/DTXD DBGU PD0/MCI0_CDA PD4/MCI0_DA3 PD3/MCI0_DA2 PD9/MCI0_CK Beeper BMS +3V3 JTAGSEL
R121=Startup in Powerdown R65 100r R64 100r R63 100r PC6/ERXER/TIOA5 PC3/ERX1/TIOA4 PC2/ERX0/TCLK3 PC7/EREFCK/TIOB5 PC5/ECRSDV/TCLK4 PC4/ETXEN/TIOB4 PC0/ETX0/TIOA3 PC1/ETX1/TIOB3 10k, 1% R121 DNP PC9/EMDIO PC8/EMDC/TCLK5 R51 1k5 C74 C76 2 1 RXER/PHYAD0 3 14 11 R119 10r 1%, 1/10W NINT/REFCLKO CRS_DV/MODE2 16 TXEN 17 TXD0 18 TXD1 10 7 RXD1/MODE1 8 RXD0/MODE0 C69 100n/16V/X7R ABLSG-25.
IC11 C7 100n/16V/X7R +3V3 SHDN R91 0r DNP 1 IN 2 REF3130 OUT X3 GND 3 R34 10k VOUT ADVREF 15p/50V GND PZ1 2 C79 VIN C9 100n/16V/X7R 3 T1 1 DMN26D0UT +3V3 2 3 100k R90 ILIM VSNS -EN STAT 9 PPAD X14 IN2 OUT IN1 5 6 7 8 100n/16V/X7R 100n/16V/X7R C12 C11 1 B1 B2 +5V-DEV C28 100n/16V/X7R DNP R16 0r +5V R17 0r 22uF/10V 5 EN 6 MODE 3 AGND 1 PGND PPAD 9 TPS62063 IC2 8 PVIN 7 AVIN Figure I.5.
