l Stamp9261 Technical Manual
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1.INTRODUCTION............................................................................................................................................... 5 2.SCOPE .................................................................................................................................................................6 3.OVERVIEW OF TECHNICAL CHARACTERISTICS.................................................................................7 3.1.CPU....................................................
c)Ethernet LEDs.............................................................................................................................................22 4.26. SYNCHRONOUS / ASYNCHRONOUS SERIAL INTERFACES (USART) ....................................................................... 23 a)USART Modes.............................................................................................................................................23 b)Signals of the serial interfaces............................
1. Introduction The Stamp is intended to be used as a small size "intelligent" display module as well as a universal Linux CPU card. It can be used anywhere where restricted energy and space requirements play a role. The Stamp9261 has all the necessary interfaces to support a huge variety of peripheral devices. Equipped with a 32-Bit parallel bus it gives fast access to a number of chips and additional devices.
2. Scope This document describes the most important hardware features of the SAM9261 Stamp9261. It includes all informations necessary to develop a customer specific hardware for the Stamp9261. The Operating System Linux is described in a further document. The manual comprises only a brief description of the AT91SAM9261 processor, as this is already described in depth in the manual of the manufacturer Atmel (document 6062).
3. Overview of Technical Characteristics 3.1. CPU Atmel AT91SAM9261 Embedded Processor featuring an ARM926EJ-S™ ARM® Thumb® Core - CPU clock 200+ MHz 16kB Instruction Cache 16kB Data Cache Memory Management Unit (MMU) 3.3V Supply Voltage, 1.2V Core Voltage 3.2. Memory - 16 or 64 MB flash memory (optional 128 MB) 32MB or 64MB SDRAM 128 KB serial Dataflash 160 KB Fast SRAM 256 Bytes EEPROM 3.3.
4. Hardware Description 4.1. Mechanics The Stamp9261 was designed as a flexible CPU-Module, which can be connected to base boards via 2x 100-pin fine-pitch low profile Hirose FX8 connectors. The size of the Stamp9261's PCB is only 53x38x4 mm fitting it in even the smallest design. While having implemented the sensible CPU, SDRAM and Flash design it still exports almost all possible CPU-Pins on it's connectors to allow a flexible design on base boards. 4.2.
4.3. Memory a) Flash memory Flash memory layout The Stamp9261 can be equipped with 16MB, 32MB, 64MB, 128MB Flash memory. This is organized in blocks of 128KB. Each block can be erased individually. • The flash memory is made up of 1 IC. In case that 128MB chips should be installed, the PIO line PC0 is used as A26, as the CPU has only 26 external address lines. Limited number of erase cycles The Flash memory consists of "Large Sector Flash-ICs" (e.g. Spansion’s S29GL256 or similar).
4.4. Battery backup The following parts of the SAM9261 Processor can be backed-up by a battery: - the Slow Clock Oscillator; - the Real Time Timer; - the Reset Controller; - the four General Purpose Backup Registers. It is recommended to always use a backup power supply (normally a battery) in order to speed up the boot-up time and to avoid reset problems. 4.5. Reset Controller (RSTC) The SAM9261 has an integrated Reset Controller which samples the backup and the core voltage (both typically at 1.
4.7. Clock Generator and Power Management Controller (PMC) a) SAM9261 Clocks The Stamp9261's SAM9261 Processor generates its necessary clocks based on two crystal oscillators: - Slow Clock (SLCK) Oscillator, running at 32768 Hz, - Main Clock Oscillator, running at 18.432 MHz.
4.8. Real-time Timer (RTT) The Real-time Timer is a 32-bit counter combined with a 16-bit prescaler running at Slow Clock (SLCK = 32768 Hz). As the RTT keeps running if only the backup supply voltage is availbale, it is used as a Real-time clock on the Stamp9261. The RTT can generate an interrupt every time the prescaler rolls over. Usually the RTT is configured to generate an interrupt every second, so the prescaler will be programmed with the value 7FFFh.
4.12. Bus Matrix The SAM9261 Processor's Bus Matrix consists of 5 masters and 5 slaves: The Bus Masters are: - ARM926EJS Core Instruction Fetch, - ARM926EJS Core Data I/O, - USB Host DMA, - LCDC-DMA, - Peripheral DMA Controller (PDC). Bus Slaves are: - internal ROM, - internal SRAM, - EBI, - internal peripherals, - LCDC and USB Host port. EBI connects to external devices. In the case of the Stamp9261 these consist in the SDRAM, the flash memory and the Ethernet Controller.
4.13. LCD Controller (LCDC) The LCD Controller of the SAM9261 processor (theoretically) supports displays with a resolution up to 2048x2048 pixels with a color depth of 24 bit per pixel, or 8 bit per color. To implement a fitting LCD, glue hardware is necessary. The LCD controller relies on a relatively simple frame buffer concept, which means that all graphics and character functions have to be implemented in software: character sets and graphic primitives are not integrated in the controller.
The "BGR" (blue-green-red) sequence in the SAM9261 LCDC is not frequently used by graphics libraries or bitmaps ("RGB" is more of a standard), neither is the use of bit 15 as an intensity bit. Of course, the first problem can be circumvented by connecting the LCDC lines to the LCD in a way deviating from the Atmel designation, that is, by exchanging the "blue" against the "red" lines.
4.18. Peripheral DMA Controller (PDC) The PDC provides both a receive and a transmit channel for each of the following full-duplex devices: - USARTs - Debug UART - SPIs - SSCs The following half duplex device uses one bidirectional DMA channel: - MCI The DMA controllers of the USB Host interface and the LCD controller have specific characteristics and are not part of the PDC.
4.19. Debug Unit (DBGU) The Debug-Unit is a simple UART which provides only RX/TX lines. It is used as a simple serial console for Firmware and Operating Systems. 4.20. JTAG Unit The JTAG unit can be used for hardware diagnostics, hardware initialization, flash memory programming, and debug purposes. The JTAG unit supports two different modes, namely the "ICE Mode", and the "Boundary Scan" mode. The Stamp9261 is normally jumpered for "ICE Mode". JTAG interface devices are available for the SAM9261.
4.21. Two-wire Interface (TWI) The TWI is also known under the expression "I²C-Bus", which is a trademark of Philips and may therefore not be used by other manufacturers. However, interoperability is guaranteed. The TWI uses only two lines, namely serial data (SDA) and serial clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in fast mode and 100 kHz in normal mode.
4.22. MultiMedia Card Interface (MCI) The Stamp9261, or its SAM9261 processor, offer full support for interfacing MultiMedia Cards. The MCI ist multiplexed with the SPI-0 port. Offering SD-Card support on devices like the Stamp9261 is not royalty-free. It is therefore not documented in this manual.
4.23. USB Host Ports (UHP) Two independent USB 2.0 Full Speed host ports are integrated in the SAM9261 processor. According to the USB specification, the term "Full Speed" denotes a transmission rate of 12 MBit/s. A "High Speed" mode (480 MBit/s) is not available with the SAM9261. a) External Parts A few external parts are required for the proper operation of the UHP: - Pull-down resistors on each line of approximately 15 kΩ.
4.24. USB Device Port (UDP) a) External Parts A few external parts are required for the proper operation of the UDP: - Pull-down resistors on each line of approximately 330 kΩ. These should be installed even if the UDP is not to be used at all in order to keep the signals from floating. - Series resistors of 27 Ω (5%) on each line. - Small capacitors (e.g. 15pF) to Ground on each line (optional). - A voltage divider on the 5V USB supply voltage V BUS converting this voltage to 3.3V, e.g.
4.25. Ethernet Controller A Davicom DM9000A 10/100 MBit Ethernet Controller is implemented on the Stamp Adaptor Board. It serves as a reference Design and a 10/100 MBit Twisted-Pair Magnetic Module (transformer plus filter). Software drivers are available for the DM9000A for Linux 2.4/2.6 and Windows CE 4.2/5.0/6.0. a) MAC Address An individual 48-bit MAC address (Ethernet hardware address) is allocated to each Stamp9261. This number is stored in flash memory as a U-Boot parameter.
4.26. Synchronous / Asynchronous Serial Interfaces (USART) Three USARTs and one UART are integrated into the SAM9261 processor. The UART ("Debug" UART) is used as the Stamp9261’s standard input/output port. It supports only the normal mode (RS232 mode). A receive and a transmit DMA channel is assigned to each USART / UART.
c) Hardware Interrupts of the Serial Interfaces There are several interrupt sources for each USART.
4.27. Synchronous Peripheral Interface (SPI) Two SPI ports, each of them with three chip selects, are available on the Stamp9261. The SPI baud rate is Master Clock (MCK) divided by a value between 1 and 255. A receive and a transmit DMA channel is assigned to each of the two SPIs. 4.28. Synchronous Serial Controller (SSC) The three Synchronous Serial Controllers of the SAM9261 processor are available which one to use depends on the multiplexing of the pins with other devices used in the application.
4.29. Parallel Input /Output Controller (PIO) The Stamp9261 has a maximum of 39 freely programmable digital I/O ports on its connectors. They can be configured independently of each other as input or output. These pins are also used by other peripheral devices. The SAM9261 Processor comes with 3 PIO controllers, each of them can manage up to 32 programmable I/O ports. Each I/O port is associated with a bit number in the 32 bit register of the user interface.
4.30. Power Management Using power management can dramatically reduce the power consumption of an Embedded Device. We assume that almost no application will use the maximum performance of the CPU and the peripherals all of the time.
5. Stamp9261 Starter Kit 5.1. Starter Kit Contents The Stamp9261 starter kit contains the following components: - Stamp9261 Stamp9261 Adaptor: Adapter board for connecting Stamp9261 and Stamp9261 Base - Panel-Card EVB: Evaluation and Prototyping Board - Wall Adapter Power Supply, Input AC 230V, Output DC 9 to 16V, min. 400 mA - Serial "Null-Modem" Cable with two 9-pin D-type Connectors - Adapter cable for accessing the Debug UART - CD with Operating System, Toolchain, and Documentation 5.2.
- Matrix keyboard Touch controller - JTAG - User Connector D-type 25pin - User Connector 26pin header (optional) - 2-contact terminal block for power supply - DC connector for power supply e) Rotary Encoder The Panel-Card EVB includes a rotary encoder with push-button which is a "Human Interface Device" well suited for many embedded applications. Generally spoken, it is a simplified replacement for a computer mouse, touch pad, or keyboard.
6. Schematics of "Panel-Card EVB" Evaluation and Prototyping Board 6.1. Disclaimer The following circuit diagram is intended for reference only and does not dispense the user from checking and applying the appropriate standards. No warranty can be granted if parts of the circuit are used in customer applications. The part of the schematics dealing with the power supply is not recommended for new designs. An updated schematics will be published in a later version of this document.
6.2.
6.3.
6.4.
6.5.
6.6.
7. Address Map (Physical address space) After the execution of the remap command the 4 GB physical address space is separated as shown in the following table. Accessing these addresses directly is only possible if the MMU (memory management unit) is deactivated. As soon as the MMU is activated the visible address space is changed completely.
8. Peripheral Identifiers The Peripheral Identifiers are used to address the corresponding peripheral unit in the interrupt controller (AIC) and in the power management controller (PMC).
9. Stamp Adaptor 9.1.
9.2. Connector Pin Description Mnemonic Description Type VCC VBATT Supply Supply GND System Supply 3.3V Backup Battery 2 ~ 3.3V. Must be connected to VCC if no battery is used.
(Connector Pin Description continued) Mnemonic Description Type Pin on X21 36 34 32 3 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PB29 PB30 PB31 PC02 PC08 PC09 PC12 PC13 PC14 PC15 PIO Line PA[20] PIO Line PA[21] PIO Line PA[22] PIO Line PA[23] PIO Line PA[24] PIO Line PA[25] PIO Line PA[26] PIO Line PA[27] PIO Line PA[28] PIO Line PA[29] PIO Line PB[29] PIO Line PB[30] PIO Line PB[31] PIO Line PC[2] PIO Line PC[8] PIO Line PC[9] PIO Line PC[12] PIO Line PC[13] PIO Line PC[14] PIO Line PC[15] I/O
(Connector Pin Description continued) Mnemonic Description Type DRXD DTXD RXD0 TXD0 SCK1 CTS1 DCD1 DSR1 DTR1 RI1 RTS1 RXD1 TXD1 SCK2 CTS2 RTS2 RXD2 TXD2 Debug UART Receive (Console Port) Debug UART Transmit (Console Port) USART #0 Receive USART #0 Transmit USART #1 Clock USART #1 CTS USART #1 DCD USART #1 DSR USART #1 DTR USART #1 RI USART #1 RTS USART #1 Receive USART #1 Transmit USART #2 Clock USART #2 CTS USART #2 RTS USART #2 Receive USART #2 Transmit I O I O I/O I I I O I I I O I/O I I I O USB DU
9.3.
b) Bus Interface
c) Wrapfield
d) Ethernet
10. DC Characteristics DC Characteristics Ambient temperature 25°C, unless otherwise indicated. Symbol Vcc Vres tres VIH Description Operating Voltage Reset Threshold Duration of Reset Pulse High-Level Input Voltage VIL Icc Low-Level Input Voltage Operating current in normal operation Battery Voltage for RTC Battery current with operating voltage turned off Vbatt Ibatt Parameter Min. 3.0 Typ. 3.3 2.9 150 2 280 Vcc+ 0.3 0.8 -0.3 max 2.0 Battery Voltage = 3V Ambient temp. = 25°C Ambient temp.
11. Stamp9261 Pin Assignment 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 I/O Interface B 1-50. 100pol.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 NBS0/A0 A2 A4 A6 A8 A10 A12 A14 BA0/A16 A18 A20 A22/NANDALE PA31/TPK15/A24 Reserved Reserved NCS0 NCS2 NCS4/CFCS0/PC4 NANDOE/NCS6/PC0 CFOE/NRD CFIOR/NBS1/NWR1 CFCE1/PC6 D0 D2 D4 D6 D8 D10 D12 D14 D16/TCLK0/PC16 D18/TCLK2/PC18 D20/TIOB0/PC20 D22/TIOB1/PC22 D24/TIOB2/PC24 D26/TK2/PC26 D28/RD2/PC28 D30/RF2/PC30 SHDN NRST RTCK NTRST TDI TDO Bus Interface 1-50.
12. Environmental Ratings Symbol Description TA Ambient temperature Relative Humidity Absolute Humidity Shock Vibration Corrosive Gas Parameter no condensation Operating Min. Max. -25 +70 Storage Min. Max. -45 +80 90 90 ≤ Humidity @TA = 60°C, 90%RH 3 0.25 not admissible 50 1.
13.
