User's Manual

26 DRAFT P440 Data Sheet / User Guide
Finally, it may be useful to clarify the directions associated with the Serial transmit (TX) and receive
(RX) lines. “User Serial TX” means transmitted by the P440 to the Host. “User Serial RX” means
received by the P440 from the Host. All user serial lines operate at 3.3v.
Fig. 15a: J11 - Locking connector
Fig. 15b: J10 – User Mezzanine connector
SPI users should take note that the SPI interrupt line is pin 4 on the User Mezzanine and pin 2 on the
locking connector.
Pin Name Function
1 SPI_MOSI SPI Master Out Slave In
2 SPI_INT SPI interrupt
3 SPI_MISO SPI Master In Slave Out
4 FPGA_GPIO_1_3.3V FPGA General Purpose IO #1, 3.3VDC
5 Fused_GND Ground
6 FPGA_GPIO_2_3.3V FPGA General Purpose IO #2, 3.3VDC
7 SPI_CLK SPI Clock
8 Fused_GND Ground
9 SPI_CS SPI Chip Select
10 User_Serial_TX User serial transmit
11 ARM_GPIO_0_3.3V ARM General Purpose IO #3, 3.3VDC
12 User_Serial_RX User serial receive
13 Fused_GND Ground
14 Fused_GND Ground
15 FPGA_GPIO_3_3.3V FPGA General Purpose IO #3, 3.3VDC
16 CAN_HIGH CAN differential high
17 VCC_Main Input power (4.5 to 48v)
18 CAN_LOW CAN differential low
Pin Name Function
1 SPI_MOSI SPI Master Out, Slave In
2
Fused_GND
Ground
3 SPI_MISO SPI Master In, Slave Out
4 SPI_INT SPI interrupt
5
Fused_GND
Ground
6 FPGA_GPIO_1_3.3V FPGA General Purpose IO #1, 3.3VDC
7 SPI_CLK SPI clock
8 FPGA_GPIO_2_3.3V FPGA General Purpose IO #2, 3.3VDC
9 SPI_CS SPI Chip Select
10
Fused_GND
Ground
11 ARM_GPIO_0_3.3V ARM General Purpose IO #0, 3.3VDC
12 User_Serial_TX User serial transmit
13
Fused_GND
Ground
14 User_Serial_Rx User serial receive
15 ARM_GPIO_1_3.3V
ARM General Purpose IO #1, 3.3VDC
16
Fused_GND
Ground
17 Power_Enable_H
Signal line to enable/disable on-board
regulators. This allows the user to turn power
to the board on and off with a single digital
control line. 0-2.1Vdc = off, 2.1Vdc to
VCC_Main = on
18 CAN_HIGH CAN differential high
19
Fused_GND
Ground
20 CAN_LOW CAN differential low
21 VCC_MAIN Input power (4.5 to 48v)