Instructions

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9.3.2 Status Register
The status register sets a bit when status changes (Refer to Table 9-2). The bit is cleared when the
condition is removed.
Bit Number Decimal Value Bit Symbol Description
0 1 CV Set high if Constant Voltage Operation
1 2 CC Set high if Constant Current Operation
2 4 NFL No fault
3 8 TW Trigger wait
4 16 AST Auto Start Enabled
5 32 FBE Foldback enable
6 64 LSC List step complete
7 128 LOC Local / Remote
8 256 UVP Ena Under voltage Protect enabled
9 512 ILC Ena Interlock Enabled
10 1024
11 2048 FBC Foldback CC mode enabled
12 4096 AVP Remote Analog Voltage Programming mode
13 8192 ACP Remote Analog Current Programming mode
14 16384 DWE The list step is active (dwelling)
15 32768 Reserved
Table 9-2: Bit Configuration of Operation
9.4 Conditional, Enable and Event Registers
9.4.1 Conditional Registers.
The condition registers show a snapshot of the power supply state at the present time. Some
faults or mode changes occur and clear quickly before the control computer can detect them.
The change may be latched in EVENT REGISTERS so the computer can detect them even if they
cleared quickly.
9.4.2 Event Registers.
Bits are sent to the Event register when a fault or mode change occurs. The bit remains set until
the control computer reads the Event register or clears it. The control computer cannot tell if the
fault or mode change occurred more than once since the last time the Event register was read.
9.4.3 Enable Register
The Status and Fault Enable registers are set by the user to enable SRQs in the event of changes
in power supply status or fault.
9.5 Service Request
A SRQ will be sent when the contents of at least one of the event registers changes from all zeroes
to any bit(s) set. When SRQ occurs, power supply sends ”!nn” message (nn-power supply address).