Datasheet

ManualsBrandsTEKTRONIX ManualsLaboratory Test EquipmentDigital 100 MHz 4-channel 2.5 null 10 null 11 Bit Digital storage (DSO), Mixed signal (MSO), Spectrum

Introduction

As electronic products become faster and more complex,

they are harder to design, verify and debug. Designers must

perform extensive veriﬁcation of their designs to ensure reliable

product operation. When problems occur, designers need to

quickly obtain insight into root cause in order to ﬁx them. The

root cause of many digital problems is quicker to pinpoint by

analyzing both the analog and digital representations of the

signal, making a mixed signal oscilloscope (MSO) ideal for

verifying and debugging digital circuits.

The Tektronix MSO2000, MSO4000, and MSO5000 Series

of mixed signal oscilloscopes combine the uncompromised

performance of a Tektronix oscilloscope with the basic

functionality of a 16-channel logic analyzer, including parallel/

serial bus protocol decoding and triggering. The Tektronix

MDO3000 and MDO4000B Series add an integrated

spectrum analyzer as well, enabling mixed domain debug

of designs including wireless connectivity. An MDO can be

considered the next generation MSO that’s designed for

systems with analog, digital, and RF signals of interest. It

should be assumed throughout this application note that any

features or capabilities referred to in MSOs are also found in

MDO products. The MSO/MDO Series are the tools of choice

for quickly debugging digital circuits using their powerful

digital triggering, high resolution acquisition capability, and

analysis tools. This application note focuses on veriﬁcation

and debugging tips to help you become more efﬁcient in

implementing your digital designs using Tektronix MSOs and

MDOs.

Digital Debugging Tips Using a Mixed

Signal or Mixed Domain Oscilloscope

Application Note

What you will learn:

How to use the basic logic analyzer functionality in the MSO and MDO Series oscilloscopes to

quickly verify and debug digital circuits.

Summary of content (16 pages)

PAGE 1
Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Application Note What you will learn: How to use the basic logic analyzer functionality in the MSO and MDO Series oscilloscopes to quickly verify and debug digital circuits. Introduction As electronic products become faster and more complex, they are harder to design, verify and debug. Designers must perform extensive verification of their designs to ensure reliable product operation.
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Application Note Figure 1. Mixed logic families (TTL & LVPECL) threshold settings on the same MSO4000B digital probe pod. The top three channels are TTL signals with a threshold of 1.40 V and the bottom two channels are LVPECL signals with a threshold of 2.00 V. Figure 2. Example of a timing acquisition on the MSO Series. Four parallel buses have been defined and decoded using the device’s clock signal.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Figure 3. Decoded data is shown in an event table which is similar to a logic analyzer’s state acquisition display. Figure 4. Probe color coding matches waveform color coding, making it easier to see which signals corresponds to which test point. Color-Coded Digital Waveform Display the clock. This means only the valid transitions on the bus are shown, excluding any transitions that happen when the data is not valid.
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Application Note Figure 5. Quick verification of the 5 V CMOS signal amplitude using measurement statistics. Figure 6. Setting the MSO digital threshold to 2.5 V for a 5 V CMOS signal. Preparing for Digital Acquisition In Figure 6, you can see the timing skew between the rising edges of the analog and digital waveforms of the same signal. The analog waveform is leading the digital waveform.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope To align the analog channels with the digital channels, the 2.5 V position on the CMOS analog waveforms are time aligned with the CMOS logic transitions which occur at the 2.5 V threshold. As shown in Figure 7, a -1.60 ns deskew is used to align the analog channel to the digital channel. This deskew process is repeated for the other analog channels.
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Application Note Figure 10. MSO Series measurement statistics verifying TTL burst signal positive and negative pulse width. The positive and negative pulse widths are more rigorously checked by changing the MSO acquisition mode from Single to Run. The positive and negative pulse statistics (mean, minimum, maximum and standard deviation) are accumulated across multiple acquisitions. You can select between 2 to 1,000 acquisitions for the measurement statistics.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope See the Complete Picture with Analog and Digital Acquisition 2.4V 1.6V 2.4V Signal 1 1.6V Signal 0 Figure 12. LVPECL signal zero with 50 ns period and signal one with 90 ns period. In this example, two Low-Voltage Positive Emitter-Coupled Logic (LVPECL) signals are verified. The 3.3 V LVPECL logic high is approximately 2.4 V and the logic low is approximately 1.6 V. Therefore, the MSO digital channels thresholds are set to 2.0 V.
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Application Note D Input Q Output 74F74 Clock Clock D Input Figure 14. Rising edge crosstalk between two LVPECL signals causing glitches. Q Output Figure 15. 74F74 D-Flip-Flop. The MSO provides the significant advantage of capturing both the signal’s digital and analog characteristics and displaying them time correlated, providing insight into the signal integrity of the digital signals. The root cause of these glitches are rising edge crosstalk between the two LVPECL signals.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Figure 17. MSO capturing a 727.3 ps clock glitch. Figure 18. Clock glitch caused by non monotonic rising clock edge. At first glance, everything looks fine with the input data appearing on the output just after the rising clock edge. The D-Flip-Flop propagation delay is noticeable with the MSO4000 Series’ 60.6 ps high-resolution MagniVu timing acquisition. The 74F74 specification is 0.
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Application Note Figure 19. D-Flip-Flop Q output error. Figure 20. D-Flip-Flop Q output error with analog insight. Figure 19 shows the MSO captured a Q output pulse width that is less than 19.2 ns. Notice that this Q output pulse width is less than the clock period. Analysis of the waveforms show that the D input is high when the rising clock edge occurred.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Acquisition System Test Signal 3F hex Signal Conditioning ADC 00 hex ADC Input MSO Ch1 Digital Bus MSO D1-D6 Bus Clock MSO D0 Figure 23. Verify sensor data acquisition system output range. Using Wave Inspector® to Quickly Verify ADC Outputs Figure 22. MSO triggering on the D-Flip-Flop data changing in the setup/hold window between cursor ‘a’ and ‘b’ around the rising clock edge.
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Application Note Figure 24. The MSO triggered on the rising edge of the input to the ADC and Wave Inspector zooms in so that parallel bus decode hex values are easily seen. The test ramp signal is on channel one. At the bottom of the display is the ADC clock on digital channel zero. The ADC digital output bus signals one through six are above the clock waveform. The ADC digital signals are grouped together into the clocked parallel bus at the center of the display. Figure 25.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Figure 26. Wave Inspector bus search finds too many 3F hex values at test signal peaks. Figure 27. Wave Inspector navigation jumps to marks at 3F hex values at test signal peak Figure 26 shows Wave Inspector searched for the maximum ADC output value of 3F hex. Wave Inspector’s bus search found 18 events. These events are gathered in three groups of search marks which are located at the test ramp signal peaks.
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Application Note Figure 28. Correct operation with one 3F hex value at each ramp peak. Figure 29. Correct operation with one 00 hex value at each ramp valley. Figure 28 shows the acquisition system analog signal conditioning gain and offset are adjusted to provide a correctly processed test ramp signal to the ADC. After the signal conditioning adjustment the ADC input waveform maximum dropped from 1.871 V to 1.838 V. Now there is only one 3F hex value at each peak of the test ramp signal as expected.
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Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope Summary The Tektronix MSO and MDO Series oscilloscopes are invaluable to designers who verify the complex interaction of digital, analog and software in their designs. Providing basic logic analyzer functionality with the ease-of-use of an oscilloscope, they feature comprehensive tools – powerful digital triggering, high resolution acquisition capability, and built-in analysis tools - to quickly verify and debug digital circuits.
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