Data Sheet

Logic Analyzer
(Requires 3-MSO option)
Vertical system digital channels
Input channels 16 digital (D15 to D0)
Thresholds Threshold per set of 8 channels
Threshold selections TTL, CMOS, ECL, PECL, User-defined
User-defined threshold range -15 V to +25 V
Maximum input voltage -20 V to +30 V
Threshold accuracy ±[130mV + 3% of threshold setting]
Input dynamic range 50 V
p-p
(threshold setting dependent)
Minimum voltage swing 500 mV
Input resistance 101 kΩ
Probe loading 8 pF
Vertical resolution 1 bit
Horizontal system digital channels
Maximum sample rate (Main) 500 MS/s (2 ns resolution)
Maximum record length (Main) 10 M
Maximum sample rate (MagniVu) 8.25 GS/s (121.2 ps resolution)
Maximum record length (MagniVu 10k centered on the trigger
Minimum detectable pulse width
(typical)
2 ns
Channel-to-channel skew (typical) 500 ps
Maximum input toggle rate 250 MHz (Maximum frequency sine wave that can accurately be reproduced as a logic square wave. Requires the use of a short
ground extender on each channel. This is the maximum frequency at the minimum swing amplitude. Higher toggle rates can be
achieved with higher amplitudes.)
Datasheet
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