Manual

C HAPTER F IVE : C HECKING W AVEFORM S TATUS
WM-RCM-E Rev D ISSUED: February 2005 65
If you enabled the setting of the ESB summary bit in STB, again nothing would occur unless you enabled
further reporting by setting the corresponding bit in the SRE register with the command *SRE 32. The
generation of a non-zero value of CMR would ripple through to MSS, generating a Service Request (SRQ).
You can read the value of CMR and simultaneously reset to zero at any time with the command CMR?. The
occurrence of a command error can also be detected by analyzing the response to *ESR?. However, if you
must survey several types of potential errors, it is usually far more efficient to enable propagation of the errors
of interest into the STB with the enable registers ESE and INE.
To summarize: a command error (CMR) sets Bit 5 of ESR if
a. Bit 5 of ESE is set, ESB of STB is also set, or
b. Bit 5 of SRE is set, MSS/RQS (Request for Service) of STB is also set and a Service Request is generated.
STATUS BYTE REGISTER (STB)
STB is the instrument’s central reporting structure. It is made up of eight single-bit summary messages, three
of which are unused, that reflect the current status of the oscilloscope’s associated data structures:
¾ Bit 0 is the INB summary bit of the Internal State Change Register. It is set if any INR bits are set,
provided they are enabled by the corresponding bit of the INE register.
¾ Bit 2 is the VAB bit, indicating that a parameter value was adapted during a previous command
interpretation.
¾ Bit 4 is the MAV bit, indicating that the interface output queue is not empty.
¾ Bit 5 is the summary bit ESB of the ESR. It is set if any of the bits of the ESR are set, provided they are
enabled by the corresponding bit of the ESE register.
¾ Bit 6 is either the MSS or RQS bit.
You can read the STB using the *STB? query. It reads and clears the STB, in which case Bit 6 is the MSS bit,
and it indicates whether the oscilloscope has any reason to request service. The response to the query
represents the binary weighted sum of the register bits. The register is cleared by *STB?, ALST?, *CLS, or
when power is applied to the instrument.
Another way to read the STB is using the serial poll (see Chapter 2). In this case, Bit 6 is the RQS bit, indicating
that the instrument has activated the SRQ line on the GPIB. The serial poll clears only the RQS bit. And the
STB’s MSS bit, and any other bits which caused MSS to be set, will remain set after the poll. These bits must be
reset.
STANDARD EVENT STATUS REGISTER (ESR)
ESR is a 16-bit register reflecting the occurrence of events. ESR bit assignments have been standardized by
IEEE 488.2. Only the lower eight bits are currently in use.
Read ESR using *ESR?. The response is the binary weighted sum of the register bits. The register is cleared
with *ESR? or ALST?, with *CLS, or when power is applied to the scope.