Manual

P ART O NE : ABOUT REMOTE CONTROL
66 ISSUED: February 2005 WM-RCM-E Rev D
Example:
The response message *ESR 160 tells you that a command error occurred and that the ESR is being read for
the first time after power-on. The value 160 can be broken down into 128 (Bit 7) plus 32 (bit 5). See the table
with the ESR command description in Part Two for the conditions corresponding to the bits set.
The Power ON bit appears only on the first *ESR? query after power-on, as the query clears the register. You
can determine this type of command error by reading the CMR with CMR?. It is not necessary that you read,
or simultaneously clear, this register in order to set the CMR bit in the ESR on the next command error.
STANDARD EVENT STATUS ENABLE REGISTER (ESE)
This register allows you to report one or more events in the ESR to the ESB summary bit in the STB.
Modify ESE with *ESE and clear it with *ESE 0, or with power-on. Read it with *ESE?.
Example: Use *ESE 4 to set bit 2 (binary 4) of the ESE Register, and to enable query errors to be reported.
SERVICE REQUEST ENABLE REGISTER (SRE)
SRE specifies which Status Byte Register summary bit or bits will bring about a service request. This register
consists of eight bits. Setting a bit allows the summary bit located at the same bit position in the SBR to
generate a service request, provided that the associated event becomes true. Bit 6 (MSS) cannot be set and is
always reported as zero in response to *SRE?.
Modify SRE with *SRE and clear it with *SRE 0, or with power-on. Read it using *SRE?.
PARALLEL POLL ENABLE REGISTER (PRE)
This specifies which Status Byte Register summary bit or bits will set the “ist” individual local message. PRE is
similar to SRE, but is used to set the parallel poll “ist” bit rather than MSS.
The value of the “ist” may also be read without a Parallel Poll via the query *IST?. The response indicates
whether or not the “ist” message has been set (values are 1 or 0).
Modify PRE with *PRE and clear it with *PRE 0, or with power-on. Read this register with *PRE?.
Example: Use *PRE 5 to set the register’s bits 2 and 0 (decimal 4 and 1).
INTERNAL STATE CHANGE STATUS REGISTER (INR)
INR reports the completion of a number of internal operations (the events tracked by this 16-bit-wide register
are listed with the INR? description in Part Two).
Read the register using INR?. The response is the binary weighted sum of the register bits. Clear the register
with INR? or ALST?, a *CLS command, or with power-on.