CC2420 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver Applications • • • • • • • 2.4 GHz IEEE 802.15.4 systems ZigBee systems Home/building automation Industrial Control Wireless sensor networks PC peripherals Consumer Electronics Product Description The CC2420 is a true single-chip 2.4 GHz IEEE 802.15.4 compliant RF transceiver designed for low power and low voltage wireless applications.
CC2420 Table of contents 1 Abbreviations_________________________________________________________________5 2 References ___________________________________________________________________6 3 Features _____________________________________________________________________7 4 Absolute Maximum Ratings _____________________________________________________8 5 Operating Conditions __________________________________________________________8 6 Electrical Specifications _____________________________________
CC2420 17 RF Data Buffering __________________________________________________________39 17.1 Buffered transmit mode _____________________________________________________39 17.2 Buffered receive mode _____________________________________________________39 17.
CC2420 40.1 40.2 40.3 40.
CC2420 1 Abbreviations ADC AES AGC ARIB BER CBC-MAC CCA CCM CFR CSMA-CA CTR CW DAC DSSS ESD ESR EVM FCC FCF FIFO FFCTRL HSSD IEEE IF ISM ITU-T - I/O I/Q kbps LNA LO LQI LSB MAC MFR MHR MIC MPDU MSDU NA NC O-QPSK PA PCB PER PHY PHR PLL PSDU QLP RAM RBW RF RSSI RX - Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Association of Radio Industries and Businesses Bit Error Rate Cipher Block Chaining Message Authentication Code Clear Channel Assessment Counter mode + CBC-MAC C
CC2420 SHR SPI TBD T/R TX VCO VGA 2 [1] - Synchronisation Header Serial Peripheral Interface To Be Decided / To Be Defined Transmit / Receive Transmit Voltage Controlled Oscillator Variable Gain Amplifier References IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2003.
CC2420 3 • • Features 2400 – 2483.5 MHz RF Transceiver • Direct Sequence Spread Spectrum (DSSS) transceiver • 250 kbps data rate, 2 MChip/s chip rate • O-QPSK with half sine pulse shaping modulation • Very low current consumption (RX: 18.8 mA, TX: 17.4 mA) • High sensitivity (-95 dBm) • High adjacent channel rejection (30/45 dB) • High alternate channel rejection (53/54 dB) • On-chip VCO, LNA and PA • Low supply voltage (2.1 – 3.
CC2420 4 Absolute Maximum Ratings Parameter Min. Max. Units Supply voltage for on-chip voltage regulator, VREG_IN pin 43. -0.3 3.6 V Supply voltage (VDDIO) for digital I/Os, DVDD3.3, pin 25. -0.3 3.6 V Supply voltage (VDD) on AVDD_VCO, DVDD1.8, etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35, 37, 44 and 48) −0.3 2.0 V Voltage on any digital I/O pin, (pin no. 21, 27-34 and 41) -0.3 VDDIO+0.3, max 3.6 V Voltage on any other pin, (pin no.
CC2420 6 Electrical Specifications Measured on CC2420 EM with transmission line balun, TA = 25 °C, voltage regulator used if nothing else stated. 6.1 and VREG_IN = 3.3 V, internal Overall Parameter Min. RF Frequency Range 2400 6.2 DVDD3.3 Typ. Max. Unit Condition / Note 2483.5 MHz Programmable in 1 MHz steps, 5 MHz steps for compliance with [1] Max. Unit Condition / Note Transmit Section Parameter Min. Typ.
CC2420 6.3 Receive Section Parameter Min. Typ. -90 -95 Max. Unit Condition / Note dBm PER = 1%, as specified by [1] Receiver Sensitivity Measured in a 50Ω single-ended load through a balun. [1] requires –85 dBm Saturation (maximum input level) 0 10 dBm PER = 1%, as specified by [1] Measured in a 50Ω single–ended load through a balun.
CC2420 Parameter Min. Frequency error tolerance -300 Typ. Max. Unit Condition / Note 300 kHz Difference between centre frequency of the received RF signal and local oscillator frequency [1] requires 200 kHz Symbol rate error tolerance 120 ppm Difference between incoming symbol rate and the internally generated symbol rate [1] requires 80 ppm Data latency 6.4 3 µs Processing delay in receiver. Time from complete transmission of SFD until complete reception of SFD, i.e.
CC2420 Parameter Min. Typ. Max. Unit Condition / Note Crystal load capacitance 12 16 20 pF 16 pF recommended 60 Ω Crystal ESR Crystal oscillator start-up time 1.0 ms Phase noise Unmodulated carrier PLL loop bandwidth −109 −117 −117 −117 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 100 kHz PLL lock time 6.
CC2420 6.8 Voltage Regulator Parameter Min. Typ. Max. Unit Condition / Note Note that the internal voltage regulator can only supply CC2420 and no external circuitry. General Input Voltage 2.1 3.0 3.6 V On the VREG_IN pin Output Voltage 1.7 1.8 1.9 V On the VREG_OUT pin Quiescent current 13 20 29 µA No current drawn from the VREG_OUT pin. Min and max numbers include 2.1 through 3.6 V input voltage 0.3 0.6 ms Start-up time 6.9 Battery Monitor Parameter Min. Typ. Max.
CC2420 Parameter Min. Typ. Max. Unit Condition / Note mA mA mA mA mA The output power is delivered differentially to a 50 Ω singled ended load through a balun, see also page 54. Current Consumption, transmit mode: P = -25 dBm P = -15 dBm P = -10 dBm P = −5 dBm P = 0 dBm 8.5 9.9 11 14 17.
CC2420 AVDD_IF1 VREG_OUT VREG_EN NC XOSC16_Q1 XOSC16_Q2 AVDD_XOSC16 42 41 40 39 38 37 R_BIAS 45 VREG_IN ATEST2 46 43 ATEST1 47 44 AVDD_CHP Pin Assignment 48 7 VCO_GUARD 1 36 NC AVDD_VCO 2 35 DVDD_RAM AVDD_PRE 3 34 SO AVDD_RF1 4 33 SI GND 5 32 SCLK RF_P 6 31 CSn TXRX_SWITCH 7 30 FIFO RF_N 8 29 FIFOP GND 9 28 CCA AVDD_SW 10 27 SFD NC 11 26 DVDD1.8 NC 12 25 DVDD3.
CC2420 Pin Pin Name Pin type Pin Description 16 17 18 19 20 21 22 23 24 25 26 27 28 29 NC AVDD_ADC DVDD_ADC DGND_GUARD DGUARD RESETn DGND DSUB_PADS DSUB_CORE DVDD3.3 DVDD1.
CC2420 8 Circuit Description AUTOMATIC GAIN CONTROL ADC DIGITAL DEMODULATOR ADC - Digital RSSI - Gain Control - Image Suppression - Channel Filtering - Demodulation - Frame synchronization LNA Serial voltage regulator CC2420 0 FREQ SYNTH 90 Serial microcontroller interface SmartRF ® CONTROL LOGIC TX/RX CONTROL DIGITAL INTERFACE WITH FIFO BUFFERS, CRC AND ENCRYPTION TX POWER CONTROL DAC Power Control PA Σ DIGITAL MODULATOR - Data spreading - Modulation Digital and Analog test interface
CC2420 and Q LO signals to the down-conversion mixers in receive mode and up-conversion mixers in transmit mode. The VCO operates in the frequency range 4800 – 4966 MHz, and the frequency is divided by two when split in I and Q. A crystal must be connected to XOSC16_Q1 and XOSC16_Q2 and provides the reference frequency for the synthesizer. A digital lock signal is available from the PLL. The 4-wire SPI serial interface is used for configuration and data buffering.
CC2420 9 Application Circuit Few external components are required for the operation of CC2420. A typical application circuit is shown in Figure 4. The external components shown are described in Table 1 and typical values are given in Table 2. Note that most decoupling capacitors are not shown on the application circuits. For the complete reference design please refer to Texas Instrument’s web site: http://www.ti.com. 9.1 Input / output matching The RF input/output is high impedance and differential.
CC2420 Ref Description C42 Voltage regulator load capacitance C61 Balun and match C62 DC block to antenna and match C71 Front-end bias decoupling and match C81 Balun and match C381 16MHz crystal load capacitor, see page 53 C391 16MHz crystal load capacitor, see page 53 L61 DC bias and match L62 DC bias and match L71 DC bias and match L81 Balun and match R451 Precision resistor for current reference generator XTAL 16MHz crystal, see page 53 Table 1.
CC2420 3.
CC2420 3.3 V Power supply C391 C381 R451 L61 L71 AVDD_XOSC16 37 XOSC16_Q2 38 XOSC16_Q1 39 NC 40 VREG_EN 41 VREG_IN 43 XTAL NC 36 2 AVDD_VCO DVDD_RAM 35 3 AVDD_PRE SO 34 4 AVDD_RF1 5 GND 6 RF_P SI 33 CC2420 7 TXRX_SWITCH 8 RF_N 9 GND SCLK 32 QLP48 RF 7x7 CSn 31 FIFO 30 Transceiver Digital Interface Folded dipole antenna VREG_OUT 42 1 VCO_GUARD AVDD_IF1 44 R_BIAS 45 ATEST2 46 ATEST1 47 AVDD_CHP 48 C42 FIFOP 29 CCA 28 10 AVDD_SW SFD 27 11 NC DVDD1.
CC2420 Item Single ended output, transmission line balun Single ended discrete balun output, Differential antenna C42 10 µF, 0.5Ω < ESR < 5Ω 10 µF, 0.5Ω < ESR < 5Ω 10 µF, 0.5Ω < ESR < 5Ω C61 Not used 0.5 pF, +/- 0.25pF, NP0, 0402 Not used C62 Not used 5.6 pF, +/- 0.25pF, NP0, 0402 Not used C71 Not used 5.6 pF, 10%, X5R, 0402 Not used C81 5.6 pF, +/- 0.25pF, NP0, 0402 0.5 pF, +/- 0.
CC2420 10 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the 2.4 GHz direct sequence spread spectrum (DSSS) RF modulation format defined in IEEE 802.15.4. For a complete description, please refer to [1]. least significant byte is transmitted first, except for security related fields where the most significant byte it transmitted first. Each symbol is mapped to one out of 16 pseudo-random sequences, 32 chips each. The symbol to chip mapping is shown in Table 3.
CC2420 TC I-phase 1 Q-phase 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 2TC Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs 11 Configuration Overview CC2420 can be configured to achieve the best performance for different applications.
CC2420 12 Evaluation Software Texas Instruments (TI) provides users of CC2420 with a software program, SmartRF® Studio (Windows interface) which may be used for radio performance and functionality evaluation. SmartRF® Studio can be downloaded from TI’s web page: http://www.ti.com. Figure 8 shows the user interface of the CC2420 configuration software. Figure 8.
CC2420 13 4-wire Serial Configuration and Data Interface CC2420 is configured via a simple 4-wire SPI-compatible interface (pins SI, SO, SCLK and CSn) where CC2420 is the slave. This interface is also used to read and write buffered data (see page 39). All address and data transfer on the SPI interface is done most significant bit first. 13.1 Pin configuration The digital inputs SCLK, SI and CSn are high-impedance inputs (no internal pullup) and should have external pull-ups if not driven.
CC2420 tsp tch tcl thd tsd tns SCLK CSn Write to register / RXFIFO: SI SO 0 0 A5 A4 A3 A2 A1 A0 S7 S6 S5 S4 S3 S2 S1 S0 X DW 15 DW 14 DW 13 DW 12 DW11 DW 10 DW9 DW 8 X DW 7 DW 6 DW 5 DW 4 DW3 DW2 DW1 DW0 X DW 7 DW 6 DW 5 DW 4 DW3 DW2 DW1 DW0 X S6 S5 S4 S3 S2 S1 S0 DR6 DR5 DR4 DR3 DR2 DR1 DR0 X Write to TXFIFO: SI SO 0 0 A5 A4 A3 A2 A1 A0 S7 S6 S5 S4 S3 S2 S1 S0 X DW 7 S7 DW 6 DW5 DW4 DW3 DW2 DW1 DW 0 S6 S5 S4 S3 S2 S
CC2420 Bit # Name Description 7 - Reserved, ignore value 6 XOSC16M_STABLE Indicates whether the 16 MHz oscillator is running or not 0 : The 16 MHz crystal oscillator is not running 1 : The 16 MHz crystal oscillator is running 5 TX_UNDERFLOW Indicates whether an FIFO underflow has occurred during transmission. Must be cleared manually with a SFLUSHTX command strobe.
CC2420 divided into three memory banks: TXFIFO (bank 0), RXFIFO (bank 1) and security (bank 2). The FIFO banks are 128 bytes each, while the security bank is 112 bytes. A6:0 is transmitted directly after the RAM/Register bit as shown in Figure 9. For RAM access, a second byte is also required before the data transfer. This byte contains B1:0 in bits 7 and 6, followed by the R/W bit (0 for read+write, 1 for read). Bits 4 through 0 are don’t care as shown in Figure 9.
CC2420 Address Byte Ordering Name Description 0x16F – 0x16C - - Not used 0x16B – 0x16A MSB LSB SHORTADR 16-bit Short address, used for address recognition. 0x169 – 0x168 MSB LSB PANID 16-bit PAN identifier, used for address recognition. 0x167 – 0x160 MSB LSB IEEEADR 64-bit IEEE address of current node, used for address recognition.
CC2420 CSn SI ADDR ADDR - - SO Status Status DATA8MSB DATA8LSB Command Strobe ADDRTXFIFO DATAADDR DATAADDR+1 DATAADDR+2 Status Status Register Read Status Status TXFIFO Write Figure 11. Multiple SPI Access Example 14 Microcontroller Interface and Pin Description When used in a typical system, CC2420 will interface to a microcontroller.
CC2420 14.2 Receive mode In receive mode, the SFD pin goes active after the start of frame delimiter (SFD) field has been completely received. If address recognition is disabled or is successful, the SFD pin goes inactive again only after the last byte of the MPDU has been received. If the received frame fails address recognition, the SFD pin goes inactive immediately. This is illustrated in Figure 13. The FIFO pin is active when there are one or more data bytes in the RXFIFO.
CC2420 c re ed te ct by te e h t d D ng Le SF Data received over RF Address recognition OK d ve ei g co re ss ted e dr le Ad omp c ti ni on U d PD eive t M rec s La yte b Preamble SFD Length MAC Protocol Data Unit (MPDU) with correct address Preamble SFD Length MAC Protocol Data Unit (MPDU) with wrong address SFD Pin FIFO Pin FIFOP Pin, if threshold higher than frame length FIFOP Pin, if threshold lower than frame length Data received over RF Address recognition fails SFD Pin FIFO Pin FIFOP P
CC2420 m m co d an N XO e ST trob s Data transmitted over RF SF Preamble SFD D tra d U itte PD sm w o M n l f st tra er La yte nd b Xu T ed itt m ns Length MAC Protocol Data Unit (MPDU) SFD Pin 12 symbol periods Automatically generated preamble and SFD Data fetched from TXFIFO CRC generated by CC2420 Figure 15. Pin activity example during transmit 14.
CC2420 I / Q Analog IF signal Digital IF Channel Filtering ADC Frequency Offset Compensation RSSI Generator Digital Data Filtering Symbol Correlators and Synchronisation Data Symbol Output Average Correlation Value (may be used for LQI) RSSI Figure 16. Demodulator Simplified Block Diagram 16 Frame Format CC2420 has hardware support for parts of the IEEE 802.15.4 frame format. This section gives a brief summary to the IEEE 802.15.
CC2420 additional zero symbols in SYNCWORD make CC2420 compliant with [1]. right) 0 7 A. If SYNCWORD = 0xA70F, CC2420 will require the incoming symbol sequence of (from left to right) 0 0 7 A. If SYNCWORD = 0xA700, CC2420 will require the incoming symbol sequence of (from left to right) 0 0 0 7 A. In reception, CC2420 synchronises to received zero-symbols and searches for the SFD sequence defined by the SYNCWORD register.
CC2420 CC2420 There is no hardware support for the data sequence number, this field must be inserted and verified by software. includes hardware address recognition, as described in the Address Recognition section on page 41. Bits: 0-2 3 4 5 6 7-9 10-11 12-13 14-15 Frame Type Security Enabled Frame Pending Acknowledge request Intra PAN Reserved Destination addressing mode Reserved Source addressing mode Figure 19.
CC2420 Length byte Data in RXFIFO n MPDU MPDU1 MPDU2 MPDUn-2 Bit number RSSI (signed) CRC / Corr 7 6 5 4 3 2 1 0 CRC Correlation value (unsigned) OK Figure 21. Data in RXFIFO when MDMCTRL0.AUTOCRC is set 17 RF Data Buffering CC2420 can be configured for different transmit and receive modes, as set in the MDMCTRL1.TX_MODE and MDMCTRL1.RX_MODE control bits. Buffered mode (mode 0) will be used for normal operation of CC2420, while other modes are available for test purposes. 17.
CC2420 Multiple data frames may be in the RXFIFO simultaneously, as long as the total number of bytes does not exceed 128. See the RXFIFO overflow section on page 33 for details on how a RXFIFO overflow is detected and signalled. 17.3 Unbuffered, serial mode Unbuffered mode should be used for evaluation / debugging purposes only. Buffered mode is recommended for all applications. In unbuffered mode, the FIFO and FIFOP pins are reconfigured as data and data clock pins.
CC2420 18 Address Recognition CC2420 includes hardware support for address recognition, as specified in [1]. Hardware address recognition may be enabled / disabled using the MDMCTRL0.ADR_DECODE control bit. Address recognition is based on the following requirements, listed from section 7.5.6.
CC2420 AUTOACK may be used for non-beacon systems as long as the frame pending field (see Figure 19) is cleared. The acknowledge frame is then transmitted 12 Bytes: symbol periods after the last symbol of the incoming frame. This is as specified by [1] for non-beacon networks.
CC2420 20 Radio control state machine CC2420 has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as SFD detected in receive mode. The radio control state machine states are shown in Figure 25. The numbers in brackets refer to the state number readable in the FSMSTATE status register. Reading the FSMSTATE status register is primarily for test / debug purposes.
CC2420 Voltage Regulator Off VREG_EN set low VREG_EN set high Wait until voltage regulator has powered up Chip Reset (pin or register) SXOSCOFF command strobe All States Crystal oscillator disabled, register access enabled, FIFO / RAM access disabled Power Down (PD) [0] SXOSCON Wait for the specified crystal oscillator start-up time, or poll the XOSC16M_STABLE status bit SRFOFF IDLE [1] N XO ST RX_CALIBRATE [2 and 40] Ov RX_OVERFLOW [17] lo erf w SFD found RX_FRAME [16 and 40] Automatic or ma
CC2420 21 MAC Security Operations (Encryption and Authentication) CC2420 features hardware IEEE 802.15.4 MAC security operations. This includes counter mode (CTR) encryption / decryption, CBC-MAC authentication and CCM encryption + authentication. All security operations are based on AES encryption [2] using 128 bit keys. Security operations are performed within the transmit and receive FIFOs on a frame basis.
CC2420 flag setting is stored in the most significant byte of the nonce. The flag byte used for encryption and authentication is then generated as shown in Figure 26. 7 - MSB in CC2420 nonce RAM 6 5 4 3 2 CTR Flag CBC Flag bits 7:6 bits 7:6 7 6 5 Res Res 0 CTR mode flag byte 4 3 2 0 0 1 The frame counter part of the nonce must be incremented for each new packet by software. 0 L 1 SECCTRL0.SEC_M 0 7 L Res CBC-MAC flag byte 6 5 4 Adata M 3 2 1 L Figure 26.
CC2420 RX in-line security operations are always performed on the first frame currently inside the RXFIFO, even if parts of this have already been read out over the SPI interface. This allows the receiver to first read the source address out to decide which key to use before doing authentication of the complete frame. In CTR or CCM mode it is of course important that bytes to be decrypted are not read out before the security operation is started. of the RXFIFO is then decrypted as specified by [1]. 21.
CC2420 Table 8 shows some examples of the time used by the security module for different operations. 21.8 Timing Mode l(a) l(m) l(MIC) Time [us] CCM 50 69 8 222 CTR - 15 - 99 CBC 17 98 12 99 Standalone - 16 - 14 Table 8. Security timing examples 22 Linear IF and AGC Settings CC2420 is based on a linear IF chain where the signal amplification is done in an analog VGA (variable gain amplifier). The gain of the VGA is digitally controlled.
CC2420 60 RSSI Register Value 40 20 0 -100 -80 -60 -40 -20 0 -20 -40 -60 RF Level [dBm] Figure 27. Typical RSSI value vs. input power 24 Link Quality Indication The link quality indication (LQI) measurement is a characterisation of the strength and/or quality of a received packet, as defined by [1]. The RSSI value described in the previous section may be used by the MAC software to produce the LQI value.
CC2420 25 Clear Channel Assessment The clear channel assessment signal is based on the measured RSSI value and a programmable threshold. The clear channel assessment function is used to implement the CSMA-CA functionality specified in [1]. CCA is valid when the receiver has been enabled for at least 8 symbol periods. Carrier sense threshold level is programmed by RSSI.CCA_THR. The threshold value can be programmed in steps of 1 dB. A CCA hysteresis can also be programmed in the MDMCTRL0.
CC2420 27 VCO and PLL Self-Calibration In order to ensure reliable operation the VCO’s bias current and tuning range are automatically calibrated every time the RX mode or TX mode is enabled, i.e. in the RX_CALIBRATE, TX_CALIBRATE and TX_ACK_CALIBRATE control states in Figure 25 on page 44. 27.1 VCO The VCO is completely integrated and operates at 4800 – 4966 MHz. The VCO frequency is divided by 2 to generate frequencies in the desired band (24002483.5 MHz). 27.
CC2420 In applications where the internal voltage regulator is not used, connect VREG_EN and VREG_IN to ground. VREG_OUT shall be left open. Note that the battery monitor will not work when the voltage regulator is not used. VREG_EN VREG_IN Regulator Enable / disable Internal bandgap voltage reference 1.25 V VREG_OUT Figure 28. Voltage regulator, simplified schematic 30 Battery Monitor The on-chip battery monitor enables monitoring the unregulated voltage on the VREG_IN pin.
CC2420 The battery monitor is controlled through the BATTMON control register. The battery monitor is enabled and disabled using the BATTMON.BATTMON_EN control bit. The voltage regulator must also be enabled when using the battery monitor. Alternatively, for a desired toggle voltage, BATTMON_VOLTAGE should be set according to: The battery monitor status bit is available in the BATTMON.BATTMON_OK status bit. This bit is high when the VREG_IN input voltage is higher than the toggle voltage Vtoggle.
CC2420 XOSC16_Q1 XOSC16_Q2 XTAL C391 C381 Figure 30. Crystal oscillator circuit Item CL= 16 pF C381 27 pF C391 27 pF Table 10. Crystal oscillator component values 32 Input / Output Matching The RF input / output is differential (RF_N and RF_P). In addition there is supply switch output pin (TXRX_SWITCH) that must have an external DC path to RF_N and RF_P. In RX mode the TXRX_SWITCH pin is at ground and will bias the LNA.
CC2420 RBW 10 kHz Ref Lvl VBW 10 kHz 3 dBm SWT 50 ms RF Att Unit 30 dB dBm 3 0 A -10 -20 -30 1AVG 1SA -40 -50 -60 -70 -80 -90 -97 Center 2.45 GHz Date: 23.OCT.2003 200 kHz/ Span 2 MHz 21:38:33 Figure 31. Single carrier output 33.2 Modulated spectrum The CC2420 has a built-in test pattern generator that can generate pseudo random sequence using the CRC generator. This is enabled by setting MDMCTRL1.TX_MODE to 3 and issues an STXON command strobe.
CC2420 RBW 100 kHz Ref Lvl VBW 100 kHz 0 dBm SWT 5 ms RF Att Unit 30 dB dBm 0 A -10 -20 -30 1AVG 1SA -40 -50 -60 -70 -80 -90 -100 Center 2.45 GHz Date: 23.OCT.2003 1 MHz/ Span 10 MHz 21:34:19 Figure 32.
CC2420 34 System Considerations and Guidelines SRD regulations 34.3 Crystal accuracy and drift International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for license free operation are allowed to operate in the 2.4 GHz band worldwide. The most important regulations are ETSI EN 300 328 and EN 300 440 (Europe), FCC CFR-47 part 15.247 and 15.249 (USA), and ARIB STD-T66 (Japan). 34.1 Frequency hopping and multichannel systems The 2.
CC2420 required to synchronisation. 34.6 Low-cost systems As the CC2420 provides 250 kbps multichannel performance without any external filters, a very low-cost system can be made. A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology. 34.7 Battery operated systems In low power applications, the CC2420 should be powered down when not being active. Extremely low power consumption may be achieved when disabling also the voltage regulator.
CC2420 • The RXCTRL1.RXBPF_LOCUR control bit should be set to 1. signal has the same phase shifts as the OQPSK sequence previously defined. The simplest way of making a PER measurement will be to use another CC2420 as the reference transmitter. However, this makes it difficult to measure the exact receiver performance. For a desired symbol sequence s0, s1, … , sn-1 of length n symbols, the desired chip sequence c0, c1, c2, …, c32n-1 of length 32n is found using table lookup from Table 3 on page 24.
CC2420 (λ/4). They are very easy to design and can be implemented simply as a “piece of wire” or even integrated into the PCB. The length of the λ/4-monopole antenna is given by: L = 7125 / f where f is in MHz, giving the length in cm. An antenna for 2450 MHz should be 2.9 cm. of the antenna. Many vendors offer such antennas intended for PCB mounting. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications.
CC2420 37 Configuration Registers The configuration of CC2420 is done by programming the 16-bit configuration registers. Complete descriptions of the registers are given in the following tables. After chip reset (from the RESETn pin or programmable through the MAIN.RESETn configuration bit), all the registers have default values as shown in the tables. Note that the MAIN register is only reset by using the pin reset RESETn.
CC2420 Address Register Register type Description 0x0E SAES S AES Stand alone encryption strobe. SPI_SEC_MODE is not required to be 0, but the encryption module must be idle. If not, the strobe is ignored.
CC2420 MAIN (0x10) - Main Control Register Bit Field Name Reset R/W Description 15 RESETn 1 R/W Active low reset of the entire circuit should be applied before doing anything else. Equivalent to using the RESETn reset pin. 14 ENC_RESETn 1 R/W Active low reset of the encryption module. (Test purposes only) 13 DEMOD_RESETn 1 R/W Active low reset of the demodulator module. (Test purposes only) 12 MOD_RESETn 1 R/W Active low reset of the modulator module.
CC2420 MDMCTRL0 (0x11) - Modem Control Register 0 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0 13 RESERVED_FRAME_MODE 0 R/W Mode for accepting reserved IEE 802.15.4 frame types when address recognition is enabled (MDMCTRL0.ADR_DECODE = 1). 0 : Reserved frame types (100, 101, 110, 111) are rejected by address recognition. 1 : Reserved frame types (100, 101, 110, 111) are always accepted by address recognition. No further address decoding is done.
CC2420 MDMCTRL1 (0x12)– Modem Control Register 1 Bit Field Name Reset R/W Description 15:11 - 0 W0 Reserved, write as 0. 10:6 CORR_THR[4:0] 20 R/W Demodulator correlator threshold value, required before SFD search. Note that on early CC2420 versions the reset value was 0. 5 DEMOD_AVG_MODE 0 R/W Frequency offset average filter behaviour. 0 : Lock frequency offset filter after preamble match 1 : Continuously update frequency offset filter.
CC2420 SYNCWORD (0x14) - Sync Word Bit 15:0 Field Name Reset R/W Description SYNCWORD[15:0] 0xA70F R/W Synchronisation word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset). SYNCWORD is used both during modulation (where 0xF’s are replaced with 0x0’s) and during demodulation (where 0xF’s are not required for frame synchronisation). In reception an implicit zero is required before the first symbol required by SYNCWORD.
CC2420 RXCTRL0 (0x16) – Receive control register 0 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0. 13:12 RXMIXBUF_CUR[1:0] 1 R/W RX mixer buffer bias current. 0: 690uA 1: 980uA (nominal) 2: 1.16mA 3: 1.44mA 11:10 HIGH_LNA_GAIN[1:0] 0 R/W Controls current in the LNA gain compensation branch in AGC High gain mode.
CC2420 RXCTRL1 (0x17) - Receive control register 1 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0. 13 RXBPF_LOCUR 0 R/W Controls reference bias current to RX bandpass filters: 0: 4 uA (Reset value) Use 1 instead 1: 3 uA Note: Recommended setting 12 RXBPF_MIDCUR 0 R/W Controls reference bias current to RX bandpass filters: 0: 4 uA (Default) 1: 3.5 uA 11 LOW_LOWGAIN 1 R/W LNA low gain mode setting in AGC low gain mode.
CC2420 FSCTRL (0x18) - Frequency Synthesizer Control and Status Bit 15:14 Field Name Reset R/W Description LOCK_THR[1:0] 1 R/W Number of consecutive reference clock periods with successful synchronisation windows required to indicate lock: 0: 64 1: 128 (recommended) 2: 256 3: 512 13 CAL_DONE 0 R Calibration has been performed since the last time the frequency synthesizer was turned on. 12 CAL_RUNNING 0 R Calibration status, '1' when calibration in progress and ‘0’ otherwise.
CC2420 SECCTRL0 (0x19) - Security Control Register Bit Field Name Reset R/W Description 15:10 - 0 W0 Reserved, write as 0 9 RXFIFO_PROTECTION 1 R/W Protection enable of the RXFIFO, see description in the RXFIFO overflow section on page 33. Should be cleared if MAC level security is not used or is implemented outside CC2420.
CC2420 SECCTRL1 (0x1A) - Security Control Register Bit Field Name Reset R/W Description 15 - 0 W0 Reserved, write as 0 14:8 SEC_TXL 0 R/W Multi-purpose length byte for TX in-line security operations: CTR : Number of cleartext bytes between length byte and the first byte to be encrypted CBC/MAC : Number of cleartext bytes between length byte and the first byte to be authenticated CCM : l(a), defining the number of bytes to be authenticated but not encrypted Stand-alone : SEC_TXL has no effect
CC2420 IOCFG0 (0x1C) – I/O Configuration Register 0 Bit Field Name Reset R/W Description 15:12 - 0 W0 Reserved, write as 0 11 BCN_ACCEPT 0 R/W Accept all beacon frames when address recognition is enabled. This bit should be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise. This bit is don't care when MDMCTRL0.ADR_DECODE = 0.
CC2420 MANFIDH (0x1F) - Manufacturer ID, Upper 16 Bit Bit Field Name Reset R/W Description 15:12 VERSION[3:0] 3 R Version number. Current version is 3. Note that previous CC2420 versions will have lower reset values. 11:0 PARTNUM[15:4] 0 R The device part number. CC2420 has part number 0x002.
CC2420 MANAND (0x21) - Manual signal AND override register1 Bit Field Name Reset R/W Description 15 VGA_RESET_N 1 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 14 BIAS_PD 1 R/W Global bias power down (1) 13 BALUN_CTRL 1 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch.
CC2420 MANOR (0x22) - Manual signal OR override register Bit Field Name Reset R/W Description 15 VGA_RESET_N 0 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 14 BIAS_PD 0 R/W Global Bias power down (1) 13 BALUN_CTRL 0 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch.
CC2420 AGCTST0 (0x24) - AGC Test Register 0 Bit Field Name Reset R/W Description 15:12 LNAMIX_HYST[3:0] 3 R/W Hysteresis on the switching between different RF front-end gain modes, defined in 2 dB steps 11:6 LNAMIX_THR_H[5:0] 25 R/W Threshold for switching between medium and high RF frontend gain mode, defined in 2 dB steps 5:0 LNAMIX_THR_L[5:0] 9 R/W Threshold for switching between low and medium RF front-end gain mode, defined in 2 dB steps AGCTST1 (0x25) - AGC Test Register 1 Bit Fie
CC2420 FSTST0 (0x27) - Frequency Synthesizer Test Register 0 Bit Field Name Reset R/W Description 15:12 - 0 W0 Reserved, write as 0 11 VCO_ARRAY_SETTLE_LONG 0 R/W When '1' this control bit doubles the time allowed for VCO settling during VCO calibration. 10 VCO_ARRAY_OE 0 R/W VCO array manual override enable. 9:5 VCO_ARRAY_O[4:0] 16 R/W VCO array override value. 4:0 VCO_ARRAY_RES[4:0] 16 R The VCO array result holds the register content of the most recent calibration.
CC2420 FSTST3 (0x2A) - Frequency Synthesizer Test Register 3 Bit Field Name Reset R/W Description 15 CHP_CAL_DISABLE 1 R/W Disable charge pump during VCO calibration when set.
CC2420 ADCTST (0x2D) - ADC Test Register Bit 15 Field Name Reset R/W Description ADC_CLOCK_DISABLE 0 R/W ADC Clock Disable 0 : Clock enabled when ADC enabled 1 : Clock disabled, even if ADC is enabled 14:8 ADC_I[6:0] 0 R Read the current ADC I-branch value. 7 - 0 W0 Reserved, write as 0. 6:0 ADC_Q[6:0] 0 R Read the current ADC Q-branch value. DACTST (0x2E) - DAC Test Register Field Name Reset R/W Description 15 - 0 W0 Reserved, write as 0.
CC2420 TOPTST (0x2F) - Top Level Test Register Bit Field Name Reset R/W Description 15:8 - 0 W0 Reserved, write as 0. 7 RAM_BIST_RUN 0 R/W Enable BIST of the RAM 0 : RAM BIST disabled, normal operation 1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1. 6 TEST_BATTMON_EN 0 R/W Enable test output of the battery monitor.
CC2420 38 Test Output Signals The two digital output pins CCA and SFD, can be set up to output test signals defined by IOCFG1.CCAMUX and IOCFG1.SFDMUX. This is summarized in Table 12 and Table 13 below. CCAMUX Signal output on CCA pin Description 0 CCA Normal operation 1 ADC_Q[0] ADC, Q-branch, LSB used for random number generation 2 DEMOD_RESYNC_LATE High one 16 MHz clock cycle each time the demodulator resynchronises late 3 LOCK_STATUS Lock status, same as FSCTRL.
CC2420 SFDMUX Signal output on SFD pin Description 0 SFD Normal operation 1 ADC_I[0] ADC, I-branch, LSB used for random number generation 2 DEMOD_RESYNCH_EARLY High one 16 MHz clock cycle each time the demodulator resynchronises early 3 LOCK_STATUS Lock status, same as FSCTRL.
CC2420 39 Package Description (QLP 48) Note: The figure is an illustration only and not to scale. Quad Leadless Package (QLP) QLP 48 Min Max D D1 E E1 6.9 6.65 6.9 6.65 7.0 6.75 7.0 6.75 7.1 6.85 7.1 6.85 e b L D2 E2 0.18 0.3 5.05 5.05 0.4 5.10 5.10 0.5 5.15 5.15 0.5 0.30 The overall packet height is 0.85 +/- 0.05 All dimensions in mm The package is compliant to JEDEC standard MO-220.
CC2420 40 Recommended layout for package (QLP 48) Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2420 EM reference design. 40.1 Package thermal properties Thermal resistance Air velocity [m/s] 0 Rth,j-a [K/W] 25.6 40.2 Soldering information Recommended soldering profile is according to IPC/JEDEC J-STD-020C.
CC2420 40.3 Plastic tube specification QLP 7x7mm antistatic tube. Tube Specification Package Tube Width Tube Height Tube Length Units per Tube QLP 48 8.5 ± 0.2 mm 2.2 +0.2/-0.1 mm 315 ± 1.25 mm 43 40.4 Carrier tape and reel specification Carrier tape and reel is in accordance with EIA Specification 481.
CC2420 42 General Information 42.1 Document History Revision Date Description/Changes SWRS041b 2007-03-19 Slightly changed optimum load impedance on Page 9 and 19 to better describe the Application circuit. SWRS041a 2006-12-18 Updated ordering information. Updated address information. Typical data latency changed from 2 to 3 us. Updates reflecting the programmable polarity of FIFO, FIFOP, SFD and CCA pins. Clarification relating to VREG_EN as digital input.
CC2420 Revision Date Description/Changes 1.2 2004-06-09 Output power range: 24 dB (was 40 dB). Deleted option for single ended external PA. Adjacent channel rejection corrected to 46 dB for + 5MHz (was 39 dB), 39 dB for –5 MHz (was 46 dB) 58 dB for +10 MHz (was 53 dB) and 55 dB for-10 MHz (was 57 dB). “image channel” deleted in text for In band spurious reception. Revision for reference [1] updated. CSMA-CA added to abbreviations. Schematic view of the IEEE 802.15.
CC2420 43 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpwrf 44 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: TI Semiconductor KnowledgeBase Home Page: support.ti.com support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: +1(972) 644-5580 Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.
CC2420 Asia Phone International Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand +886-2-23786800 Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm © 2007, Texas Instruments.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
