User's Guide Power Supply ADS5525, 27, 45, 46, 47,

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3.2.7 LED Operation
Circuit Description
Table 4. Test Points
TP DESCRIPTION
TP1 ADC common mode, input or output
depending on the setting of SW1, switch 4
TP3 THS4509 power down
TP4 ADC output enable
TP5 AGND
TP6 AGND
TP7 AGND
TP8 DGND
TP9 FPGA M0 pin; determines which FPGA logic
file to load
TP10 ADC SCLK
TP11 TPS75003 1.2 enable
TP12 TPS75003 2.5 enable
TP13 TPS75003 3.3 enable
To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4. On power up, D4 is
asserted when a successful FPGA boot up is complete. For correct EVM operation, the LED should be
asserted at all times. LED D3 is asserted when the ADC and FPGA are operating and decoding in DDR
LVDS mode, and is not asserted when the ADC is functioning in CMOS mode. Furthermore, in either DDR
LVDS mode or CMOS mode, LED D3 blinks when an ADC overrange condition occurs.
CAUTION
If LED D3 is blinking, the amplitude coming into the ADC input (J3 or J4) must
be attenuated immediately; otherwise, damage to the ADC could occur.
12 SLWU028B – January 2006 – Revised November 2006
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