Datasheet
SCAS499A − DECEMBER 1986 − REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
D Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR
) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may
be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS OUTPUT
PRE CLR CLK D Q Q
L H X X H L
H LXXLH
L LXXH
†
H
†
H H ° HHL
H H ° LLH
H H L X Q
0
Q
0
†
This configuration is nonstable; that is, it does not
persist when PRE
or CLR returns to its inactive
(high) level.
Copyright 1996, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
1CLK
1D
1CLR
V
CC
2CLR
2D
2CLK