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74AC11244

OCTAL BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

EPIC

 (Enhanced-Performance Implanted

CMOS ) 1-µm Process

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

Flow-Through Architecture Optimizes PCB

Layout

Center-Pin V

and GND Pin

Configurations Minimize High-Speed

Switching Noise

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, and Standard Plastic DIPs (NT)

description

The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and

density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The

device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE

) inputs.

When OE

is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 74AC11244 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each driver)

INPUTS

OUTPUT

OE A

L H H

L LL

HXZ

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1Y1

1Y2

1Y3

1Y4

GND

2Y1

2Y2

2Y3

2Y4

1OE

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

2OE

DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

Summary of content (15 pages)

PAGE 1
74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 D D D D D D EPIC  (Enhanced-Performance Implanted CMOS ) 1-µm Process 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outlin
PAGE 2
74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 logic symbol† 1OE 1A1 1A2 1A3 1A4 24 2OE EN 23 1 22 2 21 3 20 4 1Y1 2A1 1Y2 2A2 1Y3 1Y4 2A3 2A4 13 EN 17 9 16 10 15 11 14 12 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V MIN NOM MAX 3 5 5.5 0.9 Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t/∆v Input transition rise or fall rate V 3.85 VIL Low-level output current V 2.1 3.15 VCC = 5.5 V VCC = 3 V IOL UNIT VCC = 4.5 V VCC = 5.5 V 1.
PAGE 4
74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y MIN TA = 25°C TYP MAX MIN MAX 1.5 7.1 9.3 1.5 10.2 1.5 6.3 8.6 1.5 9.5 1.5 8 10.7 1.5 11.8 1.5 7.9 10.6 1.5 11.9 1.5 5.9 7.9 1.5 8.3 1.5 7.2 9.4 1.
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74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND LOAD CIRCUIT Output Control (low-level enabling) VCC 50% 50% 0V tPLH tPHL VOH Output S1 Open 2 × VCC GND 50% 50% 500 Ω CL = 50 pF (see Note A) Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC 50% VCC VOL VCC 0V tPZL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see N
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) 74AC11244PWRG4 ACTIVE Package Type Package Pins Package Drawing Qty TSSOP PW 24 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -40 to 85 AE244 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74AC11244DBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 74AC11244DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 74AC11244PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AC11244DBR SSOP DB 24 2000 367.0 367.0 38.0 74AC11244DWR SOIC DW 24 2000 367.0 367.0 45.0 74AC11244PWR TSSOP PW 24 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.