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74ACT11032

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCAS008C – JULY 1987 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Center-Pin V

and GND Configurations to

Minimize High-Speed Switching Noise

EPIC

(Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity at 125°C

Package Options Include Plastic

Small-Outline Packages (D), Plastic Shrink

Small-Outline Packages (DB), Plastic Thin

Shrink Small-Outline Packages (PW), and

Standard Plastic 300-mil DIPs (N)

description

This device contains four independent 2-input OR gates. It performs the Boolean function Y = A + B or

Y A • B

in positive logic.

The 74ACT11032 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

H X H

X HH

L L L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

≥

logic diagram (positive logic)

GND

D, DB, N, OR PW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (14 pages)

PAGE 1
74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008C – JULY 1987 – REVISED APRIL 1996 D D D D D D, DB, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages (D), Plastic Shrink Small-Outline Packages (DB), Plastic Thin Shrink Small-Outline Packages (PW), and Standard
PAGE 2
74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008C – JULY 1987 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.
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74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008C – JULY 1987 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA† DICC‡ MIN 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 MAX UNIT V 4.8 3.85 4.5 V IOL = 24 mA II ICC TA = 25°C TYP MAX 5.5 V IOL = 50 mA VOL MIN 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.
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74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008C – JULY 1987 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 3V 1.5 V 1.5 V 0V tPLH tPHL 500 Ω Output 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11032DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11032DR SOIC D 16 2500 333.2 345.9 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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