Datasheet

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74ACT11240

OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCAS210A − MAY 1987 − REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Inputs Are TTL-Voltage Compatible

D Flow-Through Architecture Optimizes

PCB Layout

D Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

D EPICt (Enhanced-Performance Implanted

CMOS) 1-mm Process

D 500-mA Typical Latch-Up Immunity at

125°C

D Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, and Standard

Plastic 300-mil DIPs (NT)

description

This octal buffer or line driver is designed specifically to improve both the performance and density of 3-state

memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device provides

inverting outputs and symmetrical active-low output-enable (OE

) inputs. This device features high fan-out and

improved fan-in.

The 74ACT11240 is characterized for operation from −40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE A

OUTPUT

L H L

L LH

H X Z

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2A4

2A3

2A2

2A1

2OE

1A4

1A3

1A2

1A1

1OE

2Y4

2Y3

2Y2

2Y1

1Y4

1Y3

1Y2

1Y1

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1Y1

1Y2

1Y3

1Y4

GND

2Y1

2Y2

2Y3

2Y4

1OE

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

2OE

DB, DW, OR NT PACKAGE

(TOP VIEW)

Summary of content (12 pages)

PAGE 1
74ACT11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS210A − MAY 1987 − REVISED APRIL 1996 D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes DB, DW, OR NT PACKAGE (TOP VIEW) PCB Layout 1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4 D Center-Pin VCC and GND Configurations D D D Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW) and Shrink
PAGE 2
74ACT11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS210A − MAY 1987 − REVISED APRIL 1996 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 13 24 2OE 23 1 1Y1 22 2 21 3 20 4 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 9 2Y1 17 16 10 15 11 14 12 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
74ACT11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS210A − MAY 1987 − REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 50 mA A VOH 24 mA IOH = −24 IOH = −75 mA{ TYP MAX IOL = 24 mA MIN 4.5 V 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 4.8 5.5 V IOL = 50 mA A VOL TA = 25°C MIN MAX UNIT V 3.85 4.5 V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.
PAGE 4
74ACT11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS210A − MAY 1987 − REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT Output Control (low-level enabling) 3V Input 1.5 V 1.5 V 0V tPHL tPLH VOH Output 50% VCC 50% VCC VOL 3V 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11240DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11240DWR SOIC DW 24 2000 367.0 367.0 45.
PAGE 9
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PAGE 11
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 12
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