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74ACT11374

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS217A – JULY 1987 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Eight D-Type Flip-Flops in a Single Package

3-State Bus Driving True Outputs

Full Parallel Access for Loading

Inputs Are TTL-Voltage Compatible

Flow-Through Architecture Optimizes

PCB Layout

Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

EPIC

(Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, and Standard

Plastic 300-mil DIPs (NT)

description

This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively

low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

The eight flip-flops of the 74ACT11374 are edge-triggered D-type flip-flops. On the positive transition of the clock

(CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

An output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high or low

logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus

lines significantly. The high-impedance third state provides the capability to drive bus lines in a bus-organized

system without need for interface or pullup components.

does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The 74ACT11374 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE CLK D

L ↑ H H

L ↑ LL

L LX Q

L HX Q

L ↓ XQ

H X X Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

GND

CLK

DB, DW, OR NT PACKAGE

(TOP VIEW)

Summary of content (18 pages)

PAGE 1
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 D D D D D D D D D DB, DW, OR NT PACKAGE (TOP VIEW) Eight D-Type Flip-Flops in a Single Package 3-State Bus Driving True Outputs Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up
PAGE 2
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 logic symbol† 24 OE 13 CLK 23 1D 22 2D 3D 4D 5D 6D 7D 8D EN C1 1 1D 2 21 3 20 4 17 9 16 10 15 11 14 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.
PAGE 4
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA{ IOZ II TA = 25°C TYP MAX IOL = 24 mA IOL = 75 mA{ VO = VCC or GND ICC VI = VCC or GND VI = VCC or GND, DICC} One input at 3.4 V, Ci VI = VCC or GND VO = VCC or GND MIN 4.4 4.4 5.5 V 5.4 5.
PAGE 5
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled flip flop Power dissipation capacitance per flip-flop pF CL = 50 pF, Outputs disabled TYP f = 1 MHz 107 96 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND L
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11374DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11374DWR SOIC DW 24 2000 346.0 346.0 41.
PAGE 9
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 10
PAGE 11
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11374DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11374DWR SOIC DW 24 2000 367.0 367.0 45.
PAGE 15
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PAGE 17
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
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