Datasheet
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
1OE
2OE
1B1
1B2
2B1
2B2
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
V
CCB
GND
V
CCA
RGY PACKAGE
(TOP VIEW)
Exposed
Center
Pad
The exposed center pad, if used, must be connected
only as a secondary GND or must be left electrically open.
SN74AVC4T245-Q1
www.ti.com
SCES792A –NOVEMBER 2009–REVISED OCTOBER 2012
4-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
Check for Samples: SN74AVC4T245-Q1
1
FEATURES
– 200 Mbps (Translate to 2.5 V or 1.8 V)
– 150 Mbps (Translate to 1.5 V)
• Qualified for Automotive Applications
– 100 Mbps (Translate to 1.2 V)
• AEC-Q100 Qualified With the Following
Results:
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H3B
(JESD 22 A114-A)
– Device CDM ESD Classification Level C5
(JESD 22 C101)
• Control Inputs V
IH
/V
IL
Levels Are Referenced to
V
CCA
Voltage
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to 3.6-
V Power-Supply Range
• I/Os Are 4.6-V Tolerant
• I
off
Supports Partial Power-Down-Mode
Operation
• Maximum Data Rates
– 380 Mbps (1.8-V to 3.3-V Translation)
– 200 Mbps (<1.8-V to 3.3-V Translation)
DESCRIPTION/ORDERING INFORMATION
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed
to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVC4T245 is optimized to operate with V
CCA
/V
CCB
set
at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as low as 1.2 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC4T245 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess I
CC
and I
CCZ
.
The SN74AVC4T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedance
state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.