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FEATURES

DESCRIPTION/ORDERING INFORMATION

SN74AVCAH164245

16-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES396A – JULY 2002 – REVISED JUNE 2005

• I

off

Supports Partial-Power-Down Mode

Operation

• Member of the Texas Instruments Widebus™

Family • Fully Configurable Dual-Rail Design Allows

Each Port to Operate Over the Full 1.4-V to

• DOC™ Circuitry Dynamically Changes Output

3.6-V Power-Supply Range

Impedance, Resulting in Noise Reduction

Without Speed Degradation • Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Dynamic Drive Capability Is Equivalent to

Standard Outputs With I

and I

of ± 24 mA • Latch-Up Performance Exceeds 100 mA Per

at 2.5-V V

JESD 78, Class II

• Control Inputs V

Levels Are Referenced • ESD Protection Exceeds JESD 22

to V

CCA

Voltage

– 2000-V Human-Body Model (A114-A)

• If Either V

Input Is at GND, Both Ports Are in

– 200-V Machine Model (A115-A)

the High-Impedance State

– 1000-V Charged-Device Model (C101)

• Overvoltage-Tolerant Inputs/Outputs Allow

Mixed-Voltage-Mode Data Communications

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The

A port is designed to track V

CCA

. V

CCA

accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to

track V

CCB

. V

CCB

accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage

bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCAH164245 is designed for asynchronous communication between data buses. The device

transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses are

effectively isolated.

The SN74AVCAH164245 is designed so that the control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by V

CCA

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or

pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CCA

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down. If either V

input is at GND,

then both ports are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

TSSOP – DGG Tape and reel SN74AVCAH164245GR AVCAH164245

–40°C to 85°C TVSOP – DGV Tape and reel SN74AVCAH164245VR WAH4245

VFBGA – GQL Tape and reel SN74AVCAH164245KR WAH4245

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, DOC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 • FEATURES • • • • • • Member of the Texas Instruments Widebus™ Family DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.
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SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES396A – JULY 2002 – REVISED JUNE 2005 TERMINAL ASSIGNMENTS DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCCB 2B5 2B6 GND 2B7 2B8 2DIR 2 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A
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SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.
PAGE 4
SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG and DGV packages. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX –0.5 4.6 I/O ports (A port) –0.
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www.ti.com SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES396A – JULY 2002 – REVISED JUNE 2005 Recommended Operating Conditions (1) (2) (3) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.4 3.6 V VCCB Supply voltage 1.4 3.
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SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II Control inputs IBHL (4) IBHH (5) TEST CONDITIONS IBHHO (7) Ioff A port B port A port (1) (2) (3) (4) (5) (6) (7) (8) 6 MIN TYP (3) MAX VI = VIH 1.4 V to 3.6 V 1.4 V to 3.
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SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 (1) Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ICCA TEST CONDITIONS VI = VCCI or GND, ICCB IO = 0 VI = VCCI or GND, IO = 0 MIN TYP (2) VCCA VCCB 1.6 V 1.6 V MAX 20 1.95 V 1.95 V 20 2.7 V 2.7 V 30 0V 3.6 V –40 3.6 V 0V 40 3.6 V 3.
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SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A B B A ten OE tdis OE VCCB = 1.5 V ± 0.1 V MIN VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V UNIT MAX MIN MAX MIN MAX MIN MAX 1.6 6 1.8 5.6 1.
PAGE 9
SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 Output Description The DOC™ circuitry is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit.
PAGE 10
SN74AVCAH164245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES396A – JULY 2002 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 15 pF 30 pF 30 pF 30 pF 2 kΩ 1 kΩ 500 Ω 500 Ω 0.1 V 0.15 V 0.15 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 3-Dec-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74AVCAH164245ZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SN74AVCAH164245GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AVCAH164245VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AVCAH164245ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74AVCAH164245GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74AVCAH164245VR TVSOP DGV 48 2000 367.0 367.0 38.
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PAGE 16
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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PAGE 18
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 19
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.