Datasheet

Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) (Note 3) 6.5V
Voltage
Logic Control Inputs −0.3V to +18V
At Other Input and Outputs −0.3V to (V
CC
+0.3V)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic) 260˚C
Dual-In-Line Package (ceramic) 300˚C
Surface Mount Package
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T
A
=25˚C 875 mW
ESD Susceptibility (Note 10) 800V
Operating Ratings (Notes 1, 2)
Temperature Range T
MIN
≤T
A
≤T
MAX
ADC0804LCJ −40˚C≤T
A
≤+85˚C
ADC0801/02/03/05LCN −40˚C≤T
A
≤+85˚C
ADC0804LCN 0˚C≤T
A
≤+70˚C
ADC0802/04LCWM 0˚C≤T
A
≤+70˚C
Range of V
CC
4.5 V
DC
to 6.3 V
DC
Electrical Characteristics
The following specifications apply for V
CC
=5 V
DC
,T
MIN
≤T
A
≤T
MAX
and f
CLK
=640 kHz unless otherwise specified.
Parameter Conditions Min Typ Max Units
ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj.
±
1
⁄ 4 LSB
(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8) V
REF
/2=2.500 V
DC
±
1
⁄ 2 LSB
ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj.
±
1
⁄ 2 LSB
(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8) V
REF
/2=2.500 V
DC
±
1 LSB
ADC0805: Total Unadjusted Error (Note 8) V
REF
/2-No Connection
±
1 LSB
V
REF
/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩ
ADC0804 (Note 9) 0.75 1.1 kΩ
Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 V
CC
+0.05 V
DC
DC Common-Mode Error Over Analog Input Voltage
±
1/16
±
1
⁄ 8 LSB
Range
Power Supply Sensitivity V
CC
=5 V
DC
±
10% Over
±
1/16
±
1
⁄ 8 LSB
Allowed V
IN
(+) and V
IN
(−)
Voltage Range (Note 4)
AC Electrical Characteristics
The following specifications apply for V
CC
=5 V
DC
and T
MIN
≤T
A
≤T
MAX
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
T
C
Conversion Time f
CLK
=640 kHz (Note 6) 103 114 µs
T
C
Conversion Time (Notes 5, 6) 66 73 1/f
CLK
f
CLK
Clock Frequency V
CC
=5V, (Note 5) 100 640 1460 kHz
Clock Duty Cycle 40 60 %
CR Conversion Rate in Free-Running INTR tied to WR with
8770 9708 conv/s
Mode CS =0 V
DC
,f
CLK
=640 kHz
t
W(WR)L
Width of WR Input (Start Pulse Width) CS =0 V
DC
(Note 7) 100 ns
t
ACC
Access Time (Delay from Falling C
L
=100 pF 135 200 ns
Edge of RD to Output Data Valid)
t
1H
,t
0H
TRI-STATE Control (Delay C
L
=10 pF, R
L
=10k 125 200 ns
from Rising Edge of RD to
(See TRI-STATE Test
Hi-Z State) Circuits)
t
WI
,t
RI
Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR
C
IN
Input Capacitance of Logic 5 7.5 pF
Control Inputs
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
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