Datasheet

ADC08060
www.ti.com SNAS120H –OCTOBER 2000–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC08060 uses a new, unique architecture that achieves over 7.4 effective bits at input frequencies up to
30 MHz.
The analog input signal that is within the voltage range set by V
RT
and V
RB
is digitized to eight bits. Output format
is straight binary. Input voltages below V
RB
will cause the output word to consist of all zeroes. Input voltages
above V
RB
will cause the output word to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08060 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital
outputs 2.5 clock cycles plus t
OD
later. The ADC08060 will convert as long as the clock signal is present. The
output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes just 1 mW.
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