Datasheet

LMH6702

ADC Clock

Source

Locate Clock Source

near ADC clock pin

Single

Ground

Plane

ADC

08060

Locate power supply on

the digital side of the

ADC

Locate driving amplifier

near ADC input pin

ADC08060

www.ti.com

SNAS120H –OCTOBER 2000–REVISED MARCH 2013

Figure 33. Layout Example

DYNAMIC PERFORMANCE

The ADC08060 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the

clock source driving the CLK input must exhibit less than 10 ps (rms) of jitter. For best a.c. performance, isolating

the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See

Figure 34.

It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other

signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the

analog path.

Figure 34. Isolating the ADC Clock from Digital Circuitry

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on

even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits

(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in

series with the offending digital input will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the ADC08060. Such practice may lead to conversion

inaccuracies and even to device damage.

Product Folder Links: ADC08060