Datasheet

V
IN
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
SW2
V
A
/2
CHARGE
REDISTRIBUTION
DAC
V
IN
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
SW2
V
A
/2
CHARGE
REDISTRIBUTION
DAC
ADC081C021, ADC081C027
www.ti.com SNAS447C –FEBRUARY 2008–REVISED MARCH 2013
Functional Description
The ADC081C021 and the ADC081C027 are successive-approximation analog-to-digital converters designed
around a charge-redistribution digital-to-analog converter. Unless otherwise stated, references to the
ADC081C021 in this section will apply to both the ADC081C021 and the ADC081C027.
CONVERTER OPERATION
Simplified schematics of the ADC081C021 in both track and hold operation are shown in Figure 20 and
Figure 21 respectively. In Figure 20, the ADC081C021 is in track mode. SW1 connects the sampling capacitor to
the analog input channel and SW2 equalizes the comparator inputs. The ADC is in this state for approximately
0.4µs at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when
the conversion result register is read and when the ADC is in automatic conversion mode. (see AUTOMATIC
CONVERSION MODE).
Figure 21 shows the ADC081C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2
unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract
fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the
comparator is balanced, the digital word supplied to the DAC is also the digital representation of the analog input
voltage. This digital word is stored in the conversion result register and read via the 2-wire interface.
In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result
is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of
the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that
the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum
conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,
as described in INTERNAL REGISTERS.
Figure 20. ADC081C021 in Track Mode Figure 21. ADC081C021 in Hold Mode
ANALOG INPUT
An equivalent circuit for the input of the ADC081C021 is shown in Figure 22. The diodes provide ESD protection
for the analog input. The operating range for the analog input is 0 V to V
A
. Going beyond this range will cause
the ESD diodes to conduct and result in erratic operation. For this reason, these diodes should NOT be used to
clamp the input signal.
The capacitor C1 in Figure 22 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance (R
ON
) of the multiplexer and track / hold switch and is typically 500Ω. Capacitor C2 is the
ADC081C021 sampling capacitor, and is typically 30 pF. The ADC081C021 will deliver best performance when
driven by a low-impedance source (less than 100Ω). This is especially important when using the ADC081C021 to
sample dynamic signals. A buffer amplifier may be necessary to limit source impedance. Use a precision op-amp
to maximize circuit performance. Also important when sampling dynamic signals is a band-pass or low-pass filter
to reduce noise at the input.
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Product Folder Links: ADC081C021 ADC081C027