Datasheet

ADC081C021, ADC081C027
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
V
MAX
-- Highest Conversion Register
This register holds the Highest Conversion result when in the Automatic mode. Each conversion result is
compared against the contents of this register. If the value is higher, it replaces the previous value. If the value is
lower, the register contents remain unchanged. The highest conversion value can be cleared at any time by
writing 0000h to this register. The value of this register will update automatically when the automatic conversion
mode is enabled, but is NOT updated in the normal mode.
Pointer Address 07h (Read/Write)
Default Value: 0000h
D15 D14 D13 D12 D11 D10 D9 D8
Reserved Highest Conversion [7:4]
D7 D6 D5 D4 D3 D2 D1 D0
Highest Conversion [3:0] Reserved
Bits Name Description
15:12 Reserved Always reads zeros. Zeros must be written to these bits.
11:4 Highest Conversion Highest conversion result data. D11 is MSB.
3:0 Reserved Always reads zeros. Zeros must be written to these bits.
SERIAL INTERFACE
The I
2
C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode
(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document.
The following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up
resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being
driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output
and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed. The ADC081C021 offers extended ESD tolerance (8kV HBM) for the I2C bus
pins (SCL & SDA) allowing extension of the bus across multiple boards without extra ESD protection.
Basic I
2
C Protocol
The I
2
C interface is bi-directional and allows multiple devices to operate on the same bus. The bus consists of
master devices and slave devices which can communicate back and forth over the I
2
C interface. Master devices
control the bus and are typically microcontrollers, FPGAs, DSPs, or other digital controllers. Slave devices are
controlled by a master and are typically peripheral devices such as the ADC081C021. To support multiple
devices on the same bus, each slave has a unique hardware address which is referred to as the "slave address."
To communicate with a particular device on the bus, the controller (master) sends the slave address and listens
for a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is
addressed correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus.
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is
more complicated. Please refer to High-Speed (Hs) Mode for the full details of a Hs-mode Start condition.
A Repeated Start is generated to address a different device or register, or to switch between read and write
modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the
Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 25. The bus
continues to operate in the same speed mode as before the Repeated Start condition.
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