Datasheet

1 9 1 9
Ack
by
ADC
Start by
Master
R/W
Ack
by
ADC
Frame 1
Address Byte
from Master
Frame 2
Pointer Byte
from Master
0 0 0 0 P2 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
1 9
ACK
by
ADC
NACK
by
Master
Stop
by
Master
1 9
Frame 3
Data Byte
from Master
Frame 4
Data Byte
from Master
A2 A0A1A3A4A5A6
SCL
SDA
0
SCL
(continued)
SDA
(continued)
D15 D14 D13 D12 D11 D10 D9 D8
1 9
1 9
Start by
Master
R/W
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Frame 3
Data Byte
from Master
Stop by
Master
SCL
SDA
Frame 2
Pointer Byte
from Master
ACK
by
ADC
ACK
by
ADC
ACK
by
ADC
A2
A0A1
A3A4A5A6
0 0 0 0 P2 P1 P00
ADC081C021, ADC081C027
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
Writing to an ADC Register
The following diagrams indicate the sequence of actions required for writing to an ADC081C021 Register.
Figure 33. (a) Typical Write to a 1-Byte ADC Register
Figure 34. (b) Typical Write to a 2-Byte ADC Register
QUIET INTERFACE MODE
To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved
INL and DNL performance in I
2
C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput
rate of 162ksps. Figure 35 describes how to read the conversion result register in this mode. Basically, the
Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes
that the address pointer register is set to its default value.
Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode
performance is unaffected by the Quiet Interface mode.
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Product Folder Links: ADC081C021 ADC081C027