Datasheet

D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
ACK
by
ADC
Start by
Master
N/ACK*
by
Master
SCL
SDA
Stop
by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
ADC
Frame 3
Data Byte from
ADC
R/W
A2
A0A1
A3A4A5A6
Repeat Frames
2 & 3 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
ADC081C021, ADC081C027
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
AUTOMATIC CONVERSION MODE
The automatic conversion mode configures the ADC to continually perform conversions without receiving "read"
instructions from the controller over the I
2
C interface. The mode is activated by writing a non-zero value into the
Cycle Time bits - D[7:5] - of the Configuration register (see Configuration Register). Once the ADC081C021
enters this mode, the internal oscillator is always enabled. The ADC's control logic samples the input at the
sample rate set by the cycle time bits. Although the conversion result is not transmitted by the 2-wire interface, it
is stored in the conversion result register and updates the various status registers of the device.
In automatic conversion mode, the out-of-range alert function is active and updates after every conversion. The
ADC can operate independently of the controller in automatic conversion mode. When the input signal goes "out-
of-range", an alert signal is sent to the controller. The controller can then read the status registers and determine
the source of the alert condition. Also, comparison and updating of the V
MIN
and V
MAX
registers occurs after every
conversion in automatic conversion mode. The controller can occasionally read the V
MIN
and/or V
MAX
registers to
determine the sampled input extremes. These register values persist until the user resets the V
MIN
and V
MAX
registers. These two features are useful in system monitoring, peak detection, and sensing applications.
COMMUNICATING WITH THE ADC081C021
The ADC081C021's data registers are selected by the address pointer (see Address Pointer Register). To
read/write a specific data register, the pointer must be set to that register's address. The pointer is always written
at the beginning of a write operation. When the pointer needs to be updated for a read cycle, a write operation
must precede the read operation to set the pointer address correctly. On the other hand, if the pointer is preset
correctly, a read operation can occur without writing the address pointer register. The following timing diagrams
describe the various read and write operations supported by the ADC.
Reading from a 2-Byte ADC Register
The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC081C021
Register.
Figure 29. (a) Typical Read from a 2-Byte ADC Register with Preset Pointer
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Product Folder Links: ADC081C021 ADC081C027