Datasheet

ADC081S021
SNAS308E –APRIL 2005–REVISED MARCH 2013 www.ti.com
If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is
done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and
remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully
powered-up after 16 SCLK cycles.
POWER MANAGEMENT
The ADC takes time to power-up, either after first applying V
A
, or after returning to normal mode from shutdown
mode. This corresponds to one "dummy" conversion for any SCLK frequency within the specifications in this
document. After this first dummy conversion, the ADC will perform conversions properly. Note that the t
QUIET
time
must still be included between the first dummy conversion and the second valid conversion.
When the V
A
supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As
such, one dummy conversion should be performed after start-up, as described in the previous paragraph. The
part may then be placed into either normal mode or the shutdown mode, as described in Sections Normal Mode
and Shutdown Mode.
When the ADC is operated continuously in normal mode, the maximum ensured throughput is f
SCLK
/ 20 at the
maximum specified f
SCLK
. Throughput may be traded for power consumption by running f
SCLK
at its maximum
specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before
the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in the
Typical Performance Curves section. To calculate the power consumption for a given throughput, multiply the
fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time
spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power
consumption vs. throughput is essentially linear. This is because the power consumption in the shutdown mode
is so small that it can be ignored for all practical purposes.
POWER SUPPLY NOISE CONSIDERATIONS
The charging of any output load capacitance requires current from the power supply, V
A
. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the supply. If these
variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,
discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current
into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the
substrate that will degrade noise performance if that current is large enough. The larger the output capacitance,
the more current flows through the die substrate and the greater is the noise coupled into the analog channel,
degrading noise performance.
To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice
to use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will
limit the charge and discharge current of the output capacitance and maintain noise performance.
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