Datasheet

GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
ADC081S101
SNAS310C –JANUARY 2006–REVISED MARCH 2013 www.ti.com
APPLICATIONS INFORMATION
ADC081S101 Operation
The ADC081S101 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter core. Simplified schematics of the ADC081S101 in both track and hold
operation are shown in Figure 18 and Figure 19, respectively. In Figure 18, the device is in track mode: switch
SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in
this state until CS is brought low, at which point the device moves to hold mode.
Figure 19 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining
the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-
redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.
Figure 18. ADC081S101 in Track Mode
Figure 19. ADC081S101 in Hold Mode
Using the ADC081S101
The serial interface timing diagram for the ADC is shown in Figure 3. CS is chip select, which initiates
conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion
process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a
serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for
example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold
mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from
hold mode to track mode on the 13th rising edge of SCLK (see Figure 3). It is at this point that the interval for the
T
ACQ
specification begins. In the worst case, 350 ns must pass between the 13th rising edge and the next falling
edge of SCLK. The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the
rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time t
QUIET
must be satisfied
before bringing CS low again to begin another conversion.
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