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ADC0820-N

www.ti.com

SNAS529C –JUNE 1999–REVISED MARCH 2013

ADC0820-N 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function

Check for Samples: ADC0820-N

FEATURES

KEY SPECIFICATIONS

• Built-In Track-and-Hold Function

• Resolution: 8 Bits

• No Missing Codes • Conversion Time

• No External Clocking – 2.5 µs Max (RD Mode)

• Single Supply—5 V

– 1.5 µs Max (WR-RD Mode)

• Easy Interface to All Microprocessors, or • Low Power: 75 mW Max

Operates Stand-Alone

• Total Unadjusted Error: ±½ LSB and ± 1 LSB

• Latched TRI-STATE Output

DESCRIPTION

• Logic Inputs and Outputs Meet Both MOS and

By using a half-flash conversion technique, the 8-bit

L Voltage Level Specifications

ADC0820-N CMOS A/D offers a 1.5 µs conversion

• Operates Ratiometrically or with any

time and dissipates only 75 mW of power. The half-

Reference Value Equal to or Less than V

flash technique consists of 32 comparators, a most

• 0V to 5V Analog Input Voltage Range with

significant 4-bit ADC and a least significant 4-bit

Single 5V Supply

ADC.

• No Zero or Full-Scale Adjust Required

The input to the ADC0820-N is tracked and held by

• Overflow Output Available for Cascading

the input sampling circuitry eliminating the need for

an external sample-and-hold for signals moving at

• 0.3 in. Standard Width 20-Pin PDIP

less than 100 mV/µs.

• 20-Pin PLCC

For ease of interface to microprocessors, the

• 20-Pin SOIC

ADC0820-N has been designed to appear as a

memory location or I/O port without the need for

external interfacing logic.

Connection and Functional Diagrams

Figure 1. CDIP, PDIP, Figure 2. PLCC Package

and SOIC Packages (Top View)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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ADC0820-N www.ti.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 3. Functional Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VCC) 10V Logic Control Inputs −0.2V to VCC +0.2V Voltage at Other Inputs and Output −0.2V to VCC +0.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Converter Characteristics The following specifications apply for RD mode (pin 7 = 0), VCC = 5V, VREF(+) = 5V,and VREF(−) = GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25°C.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics The following specifications apply for VCC = 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25°C. ADC0820BCN, ADC0820CCN, ADC0820BCV, ADC0820BCWM, ADC0820CCWM, ADC0820CIWM ADC0820CCJ Parameter Conditions Typ (1) VIN(1), Logical “1” Input Voltage VIN(0), Logical “0” Input Voltage VCC=5.25V VCC=4.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 AC Electrical Characteristics The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = 0V and TA = 25°C unless otherwise specified. Parameter Conditions Tested Limit (2) Typ (1) Design Limit (3) Units tCRD, Conversion Time for RD Mode Pin 7 = 0 (Figure 4) 1.6 2.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com TRI-STATE Test Circuits and Waveforms tr=20 ns t1H Circuit t1H Waveform t0H Circuit t0H Waveform tr=20 ns Timing Diagrams Note: On power-up the state of INT can be high or low. Figure 4.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Figure 5. WR-RD Mode (Pin 7 is High and tRDtI) Figure 7.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 8 Logic Input Threshold Voltage vs. Supply Voltage Conversion Time (RD Mode) vs. Temperature Figure 8. Figure 9. Power Supply Current vs. Temperature (not including reference ladder) Accuracy vs. tWR Figure 10. Figure 11. Accuracy vs. tRD Accuracy vs. tp Figure 12. Figure 13.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF Accuracy vs. [VREF=VREF(+)-VREF(-)] tI, Internal Time Delay vs. Temperature Figure 14. Figure 15. Output Current vs. Temperature Figure 16.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin Name Function 1 VIN Analog input; range =GND≤VIN≤VCC 2 DB0 TRI-STATE data output—bit 0 (LSB) 3 DB1 TRI-STATE data output—bit 1 4 DB2 TRI-STATE data output—bit 2 5 DB3 TRI-STATE data output—bit 3 6 WR-RD Mode WR: With CS low, the conversion is started on the falling edge of WR.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION GENERAL OPERATION The ADC0820-N uses two 4-bit flash A/D converters to make an 8-bit measurement (Figure 3). Each flash ADC is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. To take a full 8-bit reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash ADC).
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 18. Sampled-Data Comparator Figure 19. ADC0820-N Comparator (from MS Flash ADC) ARCHITECTURE In the ADC0820-N, one bank of 15 comparators is used in each 4-bit flash A/D converter (Figure 25). The MS (most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while the other is comparing.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 WR then RD Mode With the MODE pin tied high, the A/D will be set up for the WR-RD mode. Here, a conversion is started with the WR input; however, there are two options for reading the output data which relate to interface timing. If an interrupt driven scheme is desired, the user can wait for INT to go low before reading the conversion result (Figure 22). INT will typically go low 800 ns after WR's rising edge.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Since the MS flash ADC enters its zeroing phase at the end of a conversion (see Architecture), a new conversion cannot be started until this phase is complete. The minimum spec for this time (tP, see Figure 4 & Figure 5 & Figure 6 & Figure 7) is 500 ns. Detailed Block Diagram Figure 25.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Analog Considerations REFERENCE AND INPUT The two VREF inputs of the ADC0820-N are fully differential and define the zero to full-scale input range of the A to D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN(+) and VIN(−). By reducing VREF(VREF = VREF(+) − VREF(−)) to less than 5V, the sensitivity of the converter can be increased (i.e.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 27. ADC0820-N Input Circuit Figure 28. Analog Input, RC Network Model INPUT FILTERING It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/D's performance in most cases. In effect the ADC0820-n does not “look” at the input when these transients occur.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Typical Applications Figure 29. 8-Bit Resolution Configuration Figure 30.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 31. Telecom A/D Converter Figure 32. Multiple Input Channels Figure 33.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 Figure 34.
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ADC0820-N SNAS529C – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 35.
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ADC0820-N www.ti.com SNAS529C – JUNE 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC0820BCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 ADC0820CCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0820BCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 ADC0820CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.
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MECHANICAL DATA NFH0020A N0020A N20A (Rev G) www.ti.
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