Datasheet

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ADC0844, ADC0848

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SNAS523D –JUNE 1999–REVISED MARCH 2013

ADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer Options

Check for Samples: ADC0844, ADC0848

FEATURES

DESCRIPTION

The ADC0844 and ADC0848 are CMOS 8-bit

• Easy Interface to All Microprocessors

successive approximation A/D converters with

• Operates Ratiometrically or with 5 V

Voltage

versatile analog input multiplexers. The 4-channel or

Reference

8-channel multiplexers can be software configured for

• No Zero or Full-Scale Adjust Required

single-ended, differential or pseudo-differential modes

of operation.

• 4-Channel or 8-Channel Multiplexer with

Address Logic

The differential mode provides low frequency input

common mode rejection and allows offsetting the

• Internal Clock

analog range of the converter. In addition, the A/D's

• 0V to 5V Input Range with Single 5V Power

reference can be adjusted enabling the conversion of

Supply

reduced analog ranges with 8-bit resolution.

• Standard Width 20-Pin or 24-Pin PDIP

The A/Ds are designed to operate from the control

• 28 Pin PLCC Package

bus of a wide variety of microprocessors. TRI-STATE

output latches that directly drive the data bus permit

KEY SPECIFICATIONS

the A/Ds to be configured as memory locations or I/O

devices to the microprocessor with no interface logic

• Resolution: 8 Bits

necessary.

• Total Unadjusted Error: ±½ LSB and ± 1 LSB

• Single Supply: 5 V

• Low Power: 15 mW

• Conversion Time: 40 μs

Block Diagram

* ADC0848 shown in PDIP Package CH5-CH8 not included on the ADC0844

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 ADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer Options Check for Samples: ADC0844, ADC0848 FEATURES DESCRIPTION • • The ADC0844 and ADC0848 are CMOS 8-bit successive approximation A/D converters with versatile analog input multiplexers. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential or pseudo-differential modes of operation.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. PLCC Package (Top View) Figure 2. 20-Pin PDIP (Top View) Figure 3. 28-Pin PDIP (Top View) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VCC) 6.5V −0.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Operating Conditions (1) (2) Supply Voltage (VCC) 4.5 VDC to 6.0 VDC 0°C≤TA≤70°C ADC0844CCN, ADC0848BCN, ADC0848CCN Temperature Range (TMIN≤TA≤TMAX) (1) (2) (3) ADC0844BCJ (3), ADC0844CCJ (3), ADC0848BCV, ADC0848CCV −40°C≤TA≤85°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25°C.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage Output Current vs. Temperature Figure 4. Figure 5. Power Supply Current vs. Temperature Linearity Error vs. VREF Figure 6. Figure 7. Conversion Time vs. VSUPPLY Conversion Time vs.Temperature Figure 8. Figure 9.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unadjusted Offset Error vs. VREF Voltage Figure 10.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Timing Diagrams Read strobe must occur at least 600 ns after the assertion of interrupt to ensure reset of INTR . MA stands for MUX address. Figure 11.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Functional Description The ADC0844 and ADC0848 contain a 4-channel and 8-channel analog input multiplexer (MUX) respectively. Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended. These modes are discussed in Applications Information. The specific mode is selected by loading the MUX address latch with the proper address (see Table 1 and Table 2).
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Table 1.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 THE ANALOG INPUTS Analog Differential Voltage Inputs and Common-Mode Rejection The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between sampling the “+” input and then the “−” inputs is ½ of a clock period.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Input Current Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the “−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Figure 14. Referencing Examples - Absolute with a Reduced Span The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN (+) input which is given by: where • • VMAX = the high end of the analog input range VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 16. Differential Voltage Input 9-Bit A/D Figure 17. Span Adjust (0V ≤ VIN ≤ 3V) Diodes are 1N914 DO = all 1s if VIN(+)>VIN(−) DO = all 0s if VIN(+)
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848. Figure 21. A Stand Alone Circuit CS •WR will update the channel configuration and start a conversion. CS •RD will read the conversion data and start a new conversion without updating the channel configuration. Waiting for the end of this conversion is not necessary. A CS •WR can immediately follow the CS•RD . Figure 22.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 23.
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ADC0844, ADC0848 www.ti.com SNAS523D – JUNE 1999 – REVISED MARCH 2013 Figure 24.
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ADC0844, ADC0848 SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 18 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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MECHANICAL DATA NAM0024D www.ti.
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MECHANICAL DATA NFH0020A N0020A N20A (Rev G) www.ti.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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