Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply VSSOP 10

CS SCLK

DOUT

DIN

IN1

GND

IN4

IN3 IN2

ADC084S051

www.ti.com

SNAS261F –NOVEMBER 2004–REVISED MARCH 2013

ADC084S051 4 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter

Check for Samples: ADC084S051

FEATURES

DESCRIPTION

The ADC084S051 is a low-power, four-channel

• Specified Over a Range of Sample Rates.

CMOS 8-bit analog-to-digital converter with a high-

• Four Input Channels

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC084S051 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 500 ksps to 1 Msps. The

converter is based on a successive-approximation

KEY SPECIFICATIONS

• DNL: ±0.09 LSB (typ)

circuit. It can be configured to accept up to four input

signals at inputs IN1 through IN4.

• INL: + 0.12/−-0.062 LSB (typ)

• SNR: 49.6 dB (typ)

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

• Power Consumption:

QSPI™, MICROWIRE, and many common DSP

– 3V Supply: 2.2 mW (typ)

serial interfaces.

– 5V Supply: 7.1 mW (typ)

The ADC084S051 operates with a single supply, that

can range from +2.7V to +5.25V. Normal power

APPLICATIONS

consumption using a +3V or +5V supply is 2.2 mW

• Portable Systems

and 7.1 mW, respectively. The power-down feature

reduces the power consumption to just 0.12 µW using

• Remote Data Acquisition

a +3V supply, or 0.35 µW using a +5V supply.

• Instrumentation and Control Systems

The ADC084S051 is packaged in a 10-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C is ensured.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Specified for Sample Rate Range of:

Resolution

50 to 200 ksps 200 to 500 ksps 500 ksps to 1Msps

12-bit ADC124S021 ADC124S051 ADC124S101

10-bit ADC104S021 ADC104S051 ADC104S101

8-bit ADC084S021 ADC084S051 ADC084S101

(1) All devices are fully pin compatible.

Connection Diagram

Figure 1. VSSOP Package

See Package Number DGS0010A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 ADC084S051 4 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter Check for Samples: ADC084S051 FEATURES DESCRIPTION • • • • The ADC084S051 is a low-power, four-channel CMOS 8-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC084S051 is fully specified over a sample rate range of 500 ksps to 1 Msps.
PAGE 2
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Block Diagram IN1 . . . MUX T/H 8-Bit SUCCESSIVE APPROXIMATION ADC VA GND GND IN4 SCLK CONTROL LOGIC CS DIN DOUT Pin Descriptions and Equivalent Circuits Pin No. Pin Name Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 9 DOUT Digital data output.
PAGE 3
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Supply Voltage VA −0.3V to VA +0.
PAGE 4
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC084S051 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 50 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions Typical Limits (2) Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 8 Bits +0.12 +0.
PAGE 5
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 ADC084S051 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 50 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions Limits Typical (2) Units VA − 0.5 V (min) 0.4 V (max) 0.
PAGE 6
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC104S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +16.5 VA = +5.
PAGE 7
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 Timing Diagrams Power Down Power Up Track Power Up Hold Track Hold CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 9 8 10 SCLK Control register Control register b7 DIN b6 b5 b4 DOUT b3 b2 b1 DB7 DB6 DB5 b0 b7 DB4 DB3 DB2 DB1 b6 b5 b4 DB0 b3 b2 b1 b0 DB7 DB6 DB5 DB4 DB3 Figure 2. ADC084S051 Operational Timing Diagram Figure 3.
PAGE 8
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.
PAGE 9
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as THD = 20 ‡ log10 A f 22 + + A f 62 A f12 where • Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies.
PAGE 10
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL - VA = 3.0V INL - VA = 3.0V Figure 6. Figure 7. DNL - VA = 5.0V INL - VA = 5.0V Figure 8. Figure 9. DNL vs. Supply INL vs. Supply Figure 10. Figure 11.
PAGE 11
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 12. Figure 13. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 14. Figure 15. DNL vs. Temperature INL vs. Temperature Figure 16. Figure 17.
PAGE 12
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. Supply THD vs. Supply Figure 18. Figure 19. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 20. Figure 21. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 22. Figure 23.
PAGE 13
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Input Frequency THD vs. Input Frequency Figure 24. Figure 25. SNR vs. Temperature THD vs. Temperature Figure 26. Figure 27. SFDR vs. Supply SINAD vs. Supply Figure 28. Figure 29.
PAGE 14
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 30. Figure 31. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 32. Figure 33. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 34. Figure 35.
PAGE 15
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SFDR vs. Temperature SINAD vs. Temperature Figure 36. Figure 37. ENOB vs. Supply ENOB vs. Clock Frequency Figure 38. Figure 39. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 40. Figure 41.
PAGE 16
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 16 ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 42. Figure 43. Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps Figure 44. Figure 45. Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput Figure 46. Figure 47.
PAGE 17
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 APPLICATIONS INFORMATION ADC084S051 OPERATION The ADC084S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC084S051 in both track and hold modes are shown in Figure 48 and Figure 49, respectively.
PAGE 18
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock.
PAGE 19
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 ADC084S051 TRANSFER FUNCTION The output format of the ADC084S051 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC084S051 is VA/256. The ideal transfer characteristic is shown in Figure 50. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA/512. Other code transitions occur at steps of one LSB. 111...111 111...
PAGE 20
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ANALOG INPUTS An equivalent circuit for one of the ADC084S051's input channels is shown in Figure 52. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, these ESD diodes should NOT be used to clamp the input signal.
PAGE 21
ADC084S051 www.ti.com SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 Power Management When the ADC084S051 is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 8 MHz and performing fewer conversions per unit time, putting the ADC084S051 into shutdown mode between conversions. A plot of typical power consumption versus throughput is shown in the Typical Performance Characteristics section.
PAGE 22
ADC084S051 SNAS261F – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC084S051CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC084S051CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC084S051CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
PAGE 26
PAGE 27
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.