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ADC08L060

www.ti.com

SNAS167G –MAY 2002–REVISED MARCH 2013

ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal

Sample-and-Hold

Check for Samples: ADC08L060

FEATURES

DESCRIPTION

The ADC08L060 is a low-power, 8-bit, monolithic

• Single-ended input

analog-to-digital converter with an on-chip track-and-

• Internal sample-and-hold function

hold circuit. Optimized for low cost, low power, small

• Low voltage (single +3V) operation

size and ease of use, this product operates at

conversion rates of 10 MSPS to 60 MSPS while

• Small package

consuming just 0.65 mW per MHz of clock frequency,

• Power-down feature

or 39 mW at 60 MSPS. Raising the PD pin puts the

ADC08L060 into a Power Down mode where it

KEY SPECIFICATIONS

consumes about 1 mW.

• Resolution 8 bits

The unique architecture achieves 7.6 Effective Bits.

• Conversion rate 60 MSPS

The ADC08L060 is resistant to latch-up and the

outputs are short-circuit proof. The top and bottom of

• DNL ±0.25 LSB (typ)

the ADC08L060s reference ladder are available for

• INL +0.5/−0.2 LSB (typ)

connections, enabling a wide range of input

• SNR (10.1 MHz) 48 dB (typ)

possibilities. The digital outputs are TTL/CMOS

compatible with a separate output power supply pin

• ENOB (10.1 MHz) 7.6 bits (typ)

to support interfacing with 1.8V to 3V logic. The

• THD (10.1 MHz) −57 dB (typ)

output coding is straight binary and the digital inputs

• Latency 5 Clock Cycles

(CLK and PD) are TTL/CMOS compatible.

• No missing codes Ensured

The ADC08L060 is offered in a 24-lead plastic

• Power Consumption

package (TSSOP) and is specified over the industrial

temperature range of −40°C to +85°C.

– Operating 0.65 mW/MSPS (typ)

– Power Down Mode 1.0 mW (typ)

APPLICATIONS

• Digital Imaging

• Set-top boxes

• Portable Instrumentation

• Communication Systems

• X-ray imaging

• Viterbi decoders

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold Check for Samples: ADC08L060 FEATURES DESCRIPTION • • • • • The ADC08L060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-andhold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Table 1. Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 9 VRM Mid-point of the reference ladder.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (VA) 3.8V Driver Supply Voltage (VDR) VA +0.3V −0.3V to VA Voltage on Any Input or Output Pin Reference Voltage (VRT, VRB) VA to AGND −0.05V to (VA + 0.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Converter Electrical Characteristics The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) Symbol Parameter Conditions Typical Limits (4) Units (Limits) (4) DC ACCURACY INL Integral Non-Linearity +0.5 −0.2 +1.9 −1.35 LSB (max) LSB (min) DNL Differential Non-Linearity ±0.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2) (3) Symbol Parameter Typical Conditions (4) Limits (4) Units (Limits) CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage VDR = VA = 3.6V 2.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Timing Diagram Figure 1.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated 10 INL INL vs Temperature Figure 2. Figure 3. INL vs Supply Voltage, VA INL vs Sample Rate Figure 4. Figure 5. INL vs Clock Duty Cycle DNL Figure 6. Figure 7.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated DNL vs Temperature DNL vs Supply Voltage, VA Figure 8. Figure 9. DNL vs Sample Rate DNL vs Clock Duty Cycle Figure 10. Figure 11. SNR, SINAD and SFDR vs Temperature SNR, SINAD and SFDR vs Supply Voltage, VA Figure 12. Figure 13.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated 12 SNR, SINAD and SFDR vs Sample Rate SNR, SINAD and SFDR vs Input Frequency Figure 14. Figure 15. SNR, SINAD and SFDR vs Clock Duty Cycle Distortion vs Temperature Figure 16. Figure 17. Distortion vs Supply Voltage, VA Distortion vs Sample Rate Figure 18. Figure 19.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated Distortion vs Input Frequency Distortion vs Clock Duty Cycle Figure 20. Figure 21. Power Consumption (Active) vs. Sample Rate (fIN = d.c.) Power Consumption (Active) vs. Sample Rate (fIN = d.c.) Figure 22. Figure 23. Power Consumption (Active) vs. Sample Rate (fIN = 1 MHz) Power Consumption (Active) vs.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated 14 Spectral Response @ fIN = 10 MHz Spectral Response @ fIN = 29 MHz Figure 26. Figure 27. Spectral Response @ fIN = 75 MHz Spectral Response @ fIN = 98.9 MHz Figure 28. Figure 29.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC08L060 uses a unique architecture that achieves over 7 effective bits at input frequencies up to and beyond Nyquist. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com The reference bias circuit of Figure 30 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide reference voltage range. Better reference stability can be achieved by driving the reference pins with low impedance sources. The circuit of Figure 31 will allow a more accurate setting of the reference voltages.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material. A resistor value should be chosen between 10Ω and 47Ω and the capacitor value chose according to the formula (6) This will provide optimum SNR performance.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08L060 power pins.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 The DR GND connection to the ground plane should not use the same feedthrough used by other ground connections. High power digital components should not be located on or near a straight line between the ADC or any linear component and the power supply area as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com Single Ground Plane ADC Clock Source Locate driving amplifier near ADC input pin RF Locate Clock Source near ADC clock pin RIN R C LMH6702 ADC 08L060 Locate power supply on the digital side of the ADC Figure 33. Layout Example The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g.
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ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 5 pF.
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ADC08L060 SNAS167G – MAY 2002 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision F (March 2013) to Revision G • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC08L060CIMTX/NOPB TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC08L060CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.
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