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ADC10061, ADC10062, ADC10064

www.ti.com

SNAS069E –JUNE 1999–REVISED MARCH 2013

ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and

Sample/Hold

Check for Samples: ADC10061, ADC10062, ADC10064

FEATURES

DESCRIPTION

NOTE: The ADC10061 and ADC10062 are obsolete.

• Built-in Sample-and-Hold

They are described here for reference only.

• Single +5V Supply

Using an innovative, patented multistep* conversion

• No External Clock Required

technique, these CMOS analog-to-digital converters

• Speed Adjust Pin for Faster Conversions

offer sub-microsecond conversion times yet dissipate

(ADC10062 and ADC10064). See ADC10662/4

a maximum of only 235 mW. These converters

for High Speed Ensured Performance.

perform 10-bit conversions in two lower-resolution

“flashes”, yielding a fast A/D without the cost, power

APPLICATIONS consumption, and other problems associated with

true flash approaches.

• Digital Signal Processor Front Ends

The analog input voltage is sampled and held by an

• Instrumentation

internal sampling circuit. Input signals at frequencies

• Disk Drives

from DC to over 200 kHz can, therefore, be digitized

• Mobile Telecommunications

accurately without the need for an external sample-

and-hold circuit.

KEY SPECIFICATIONS

The ADC10062 and ADC10064 include a “speed-up”

• Conversion Time 600 ns Typical, 900 ns Max

pin. Connecting an external resistor between this pin

and ground reduces the typical conversion time to as

• Sampling Rate 800 kHz

little as 350 ns with only a small increase in linearity

• Low Power Dissipation 235 mW (Max)

error.

• Total Unadjusted Error ±1.0 LSB (Max)

For ease of interface to microprocessors, the

• No Missing Codes Over Temperature

ADC10061, ADC10062, and ADC10064 have been

designed to appear as a memory location or I/O port

without the need for external interface logic.

*U.S. Patent Number 4918449

Simplified Block Diagram

*ADC10061 Only, **ADC10062 and ADC10064 Only, ***ADC10064 Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold Check for Samples: ADC10061, ADC10062, ADC10064 FEATURES DESCRIPTION • • • • NOTE: The ADC10061 and ADC10062 are obsolete. They are described here for reference only. 1 2 Built-in Sample-and-Hold Single +5V Supply No External Clock Required Speed Adjust Pin for Faster Conversions (ADC10062 and ADC10064).
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Connection Diagram This device is obsolete; shown for reference only. Figure 1. Top View This device is obsolete; shown for reference only. Figure 2. Top View Figure 3.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 NOTE: The ADC10061 and ADC10062 are obsolete; shown for reference only. PIN DESCRIPTIONS Pin Function Description DVCC, AVCC Digital and analog positive supply voltage inputs. Connect both to the same voltage source, but bypass separately with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to ground at each pin. INT Active low interrupt output.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Supply Voltage (V+ = AVCC = DVCC) −0.3V to +6V −0.3V to V+ + 0.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 Converter Characteristics (continued) The following specifications apply for V+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMin to TMax; all other limits TA = TJ = +25°C. Symbol Parameter Conditions Typical (1) Limit (2) Units (Limit) Power Supply Sensitivity V+ = 5V ±5%, VREF = 4.5V V+ = 5V ±10%, VREF = 4.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics (continued) The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 Timing Diagrams The conversion time (tCONV) is set by the internal timer. Figure 4. Mode 1 The conversion time (tCRD) includes the sampling time and is determined by the internal timer. Figure 5.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 8 Zero (Offset) Error vs. Reference Voltage Linearity Error vs. Reference Voltage Figure 6. Figure 7. Analog Supply Current vs. Temperature Digital Supply Current vs. Temperature Figure 8. Figure 9. Conversion Time vs. Temperature Conversion Time vs. Temperature Figure 10. Figure 11.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Conversion Time vs. Speed-Up Resistor (ADC10062 and ADC10064 Only) Conversion Time vs. Speed-Up Resistor (ADC10062 and ADC10064 Only) Figure 12. Figure 13. Spectral Response with100 kHz Sine Wave Input Spectral Response with 100 kHz Sine Wave Input Figure 14. Figure 15. Signal-to-Noise + THD Ratio vs. Signal Frequency Linearity Change vs.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Linearity Change vs. Speed-Up Resistor (ADC10062 and ADC10064 Only) Linearity Error Change vs. Sample Time Figure 18. Figure 19. Functional Description The ADC10061 and the ADC10062 are obsolete. They are discussed here for reference only.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the multistep conversion technique used in the ADC10061, ADC10062, and ADC10064 needs only a small fraction of the number of comparators that would be required for a traditional flash converter, and far fewer than would be used in a conventional half-flash approach.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION MODES OF OPERATION The ADC10061, ADC10062, and ADC10064 have two basic digital interface modes. Figure 4 and Figure 5 are timing diagrams for the two modes. The ADC10062 and ADC10064 have input multiplexers that are controlled by the logic levels on pins S0 and S1 when S/H goes low. Table 1 is a truth table showing how the input channels are assigned.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 Since the resistance between the two reference inputs can be as low as 400Ω, the voltage source driving the reference inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. Each reference pin should be bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Because they incorporate a direct sample/hold control input, the ADC10061, ADC10062, and ADC10064 are suitable for use in DSP-based systems. The S/H input allows synchronization of the A/D converter to the DSP system's sampling rate and to other ADC10061s, ADC10062s, and ADC10064s. POWER SUPPLY CONSIDERATIONS The ADC10061, ADC10062, and ADC10064 are designed to operate from a +5V (nominal) power supply.
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ADC10061, ADC10062, ADC10064 www.ti.com SNAS069E – JUNE 1999 – REVISED MARCH 2013 where • S/(N + D) is the ratio of signal to noise and distortion, which can vary with frequency (1) As an example, an ADC10061 with a 5 VP-P, 100 kHz sine wave input signal will typically have a signal-to-noiseplus-distortion ratio of 59.2 dB, which is equivalent to 9.54 effective bits.
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ADC10061, ADC10062, ADC10064 SNAS069E – JUNE 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 16 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC10064CIWMX/NOPB Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.4 3.2 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10064CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.
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