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ADC10065

www.ti.com

SNAS225H –JULY 2003–REVISED APRIL 2013

ADC10065 10-Bit 65 MSPS 3V A/D Converter

Check for Samples: ADC10065

FEATURES

DESCRIPTION

The ADC10065 is a monolithic CMOS analog-to-

• Single +3.0V Operation

digital converter capable of converting analog input

• Selectable 2 V

P-P

, 1.5 V

P-P

, or 1 V

P-P

Full-scale

signals into 10-bit digital words at 65 Megasamples

Input

per second (MSPS). This converter uses a

• 400 MHz −3 dB Input Bandwidth

differential, pipeline architecture with digital error

correction and an on-chip sample-and-hold circuit to

• Low Power Consumption

provide a complete conversion solution, and to

• Standby Mode

minimize power consumption, while providing

• On-Chip Reference and Sample-and-Hold

excellent dynamic performance. A unique sample-

Amplifier

and-hold stage yields a full-power bandwidth of 400

MHz. Operating on a single 3.0V power supply, this

• Offset Binary or Two’s Complement Data

device consumes just 68.4 mW at 65 MSPS,

Format

including the reference current. The Standby feature

• Separate Adjustable Output Driver Supply to

reduces power consumption to just 14.1 mW.

Accommodate 2.5V and 3.3V Logic Families

The differential inputs provide a full scale selectable

• 28-pin TSSOP Package

input swing of 2.0 V

P-P

, 1.5 V

P-P

, 1.0 V

P-P

, with the

possibility of a single-ended input. Full use of the

APPLICATIONS

differential input is recommended for optimum

performance. An internal +1.2V precision bandgap

• Ultrasound and Imaging

reference is used to set the ADC full-scale range, and

• Instrumentation

also allows the user to supply a buffered referenced

• Cellular Base Stations/Communications

voltage for those applications requiring increased

Receivers

accuracy. The output data format is user choice of

offset binary or two’s complement.

• Sonar/Radar

• xDSL

This device is available in the 28-lead TSSOP

package and will operate over the industrial

• Wireless Local Loops

temperature range of −40°C to +85°C.

• Data Acquisition Systems

• DSP Front Ends

KEY SPECIFICATIONS

• Resolution 10 Bits

• Conversion Rate 65 MSPS

• Full Power Bandwidth 400 MHz

• DNL ±0.3 LSB (typ)

• SNR (f

= 11 MHz) 59.6 dB (typ)

• SFDR (f

= 11 MHz) −80 dB (typ)

• Power Consumption, 65 MHz 68.4 mW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 ADC10065 10-Bit 65 MSPS 3V A/D Converter Check for Samples: ADC10065 FEATURES DESCRIPTION • • The ADC10065 is a monolithic CMOS analog-todigital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS).
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 1.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Pin Name Equivalent Circuit Description ANALOG I/O 12 VIN− Inverting analog input signal. With a 1.2V reference the full-scale input signal level is a differential 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the fullscale input signal level is a differential 1.0 VP-P.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin No. Pin Name Equivalent Circuit Description 16–20, 23–27 D0–D9 Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. 2, 9, 10 VDDA Positive analog supply pins. These pins should be connected to a quiet 3.0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) VDDA, VDDIO 3.9V −0.3V to VDDA or VDDIO +0.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. (1) (2) (3) (4).
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. (1) Parameter Test Conditions T = 25°C Min 2 (2) Typ (2) 3.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Timing Diagram Figure 3. Clock and Data Timing Diagram Transfer Characteristics Figure 4. Input vs.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. DNL DNL vs. fCLK Figure 5. Figure 6. DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature Figure 7. Figure 8. INL INL vs. fCLK Figure 9. Figure 10.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. 12 INL vs. Clock Duty Cycle SNR vs. VDDIO Figure 11. Figure 12. SNR vs. VDDA SNR vs. fCLK Figure 13. Figure 14. INL vs. Temperature SNR vs. Clock Duty Cycle Figure 15. Figure 16.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. SNR vs. Temperature THD vs. VDDA Figure 17. Figure 18. THD vs. VDDIO THD vs. fCLK Figure 19. Figure 20. SNR vs. IRS THD vs. IRS Figure 21. Figure 22.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. 14 SINAD vs. VDDA SINAD vs. VDDIO Figure 23. Figure 24. THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 25. Figure 26. THD vs. Temperature SINAD vs. Temperature Figure 27.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. SINAD vs. fCLK SFDR vs. VDDIO Figure 29. Figure 30. SINAD vs. IRS SFDR vs. fCLK Figure 31. Figure 32. SFDR vs. VDDA SFDR vs. IRS Figure 33. Figure 34.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = External 1.2V, fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. SFDR vs. Clock Duty Cycle Spectral Response @ 11 MHz Input Figure 35. Figure 36. SFDR vs. Temperature Spectral Response @ 32 MHz Input Figure 37. Figure 38. Power Consumption vs.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode, each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin (pin 5), and be centered around VCM and be 180° out of phase with each other.
PAGE 18
ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com CLK PIN The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the frequency range indicated in AC Electrical Characteristics with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. The CLK signal also drives an internal state machine.
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ADC10065 www.ti.com SNAS225H – JULY 2003 – REVISED APRIL 2013 APPLICATION SCHEMATICS The following figures show simple examples of using the ADC10065. Figure 42 shows a typical differentially driven input. Figure 43 shows a single ended application circuit. Figure 42. A Simple Application Using a Differential Driving Source Figure 43.
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ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision G (April 2013) to Revision H • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Jun-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC10065CIMTX/NOPB Package Package Pins Type Drawing TSSOP PW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.8 B0 (mm) K0 (mm) P1 (mm) 10.2 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10065CIMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.
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