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SCLK

DOUT

DIN

IN1

GND

ADC102S021

IN2

ADC102S021

www.ti.com

SNAS281G –FEBRUARY 2005–REVISED MARCH 2013

ADC102S021 2 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

Check for Samples: ADC102S021

FEATURES

DESCRIPTION

The ADC102S021 is a low-power, two-channel

• Specified Over a Range of Sample Rates.

CMOS 10-bit analog-to-digital converter with a high-

• Two Input Channels

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC102S021 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 50 ksps to 200 ksps. The

converter is based on a successive-approximation

APPLICATIONS

• Portable Systems

circuit. It can be configured to accept one or two input

signals at inputs IN1 and IN2.

• Remote Data Acquisition

• Instrumentation and Control Systems

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

KEY SPECIFICATIONS

serial interfaces.

• DNL: ± 0.13 LSB (typ)

The ADC102S021 operates with a single supply that

• INL: ± 0.13 LSB (typ)

can range from +2.7V to +5.25V. Normal power

• SNR: 61.8 dB (typ)

consumption using a +3V or +5V supply is 1.94 mW

• Power Consumption

and 6.9 mW, respectively. The power-down feature

reduces the power consumption to just 0.12 µW using

– 3V Supply: 1.94mW (typ)

a +3V supply, or 0.47 µW using a +5V supply.

– 5V Supply: 6.9 mW (typ)

The ADC102S021 is packaged in an 8-lead VSSOP

package. Operation is specified over the industrial

temperature range of −40°C to +85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Specified for Sample Rates of:

Resolution

50 to 200 ksps 200 to 500 ksps 500 ksps to 1Msps

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Figure 1. VSSOP Package

See Package Number DGK0008A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 ADC102S021 2 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter Check for Samples: ADC102S021 FEATURES DESCRIPTION • • • • The ADC102S021 is a low-power, two-channel CMOS 10-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC102S021 is fully specified over a sample rate range of 50 ksps to 200 ksps.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Block Diagram IN1 MUX T/H IN2 10-BIT SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT Figure 2. Table 2. Pin Descriptions and Equivalent Circuits Pin No. Name Description ANALOG I/O 5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 7 DOUT Digital data output.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA Voltage on Any Pin to GND −0.3V to VA +0.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com ADC102S021 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions Typ Limits (1) Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 10 Bits +0.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 ADC102S021 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Typ Limits (1) Units ISOURCE = 200 µA VA − 0.03 VA − 0.5 V (min) ISOURCE = 1 mA VA − 0.1 ISINK = 200 µA 0.03 0.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com ADC102S021 Timing Specifications (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Figure 5. ADC102S021 Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 6. SCLK and CS Timing Parameters Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components that are present at the output and are not present at the input and result from two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V Figure 7. Figure 8. DNL - VA = 5.0V INL - VA = 5.0V Figure 9. Figure 10. DNL vs. Supply INL vs. Supply Figure 11. Figure 12.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 10 DNL vs. Clock Frequency INL vs. Clock Frequency Figure 13. Figure 14. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 15. Figure 16. DNL vs. Temperature INL vs. Temperature Figure 17. Figure 18.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. SNR vs. Supply THD vs. Supply Figure 19. Figure 20. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 21. Figure 22. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 23. Figure 24.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 12 SNR vs. Input Frequency THD vs. Input Frequency Figure 25. Figure 26. SNR vs. Temperature THD vs. Temperature Figure 27. Figure 28. SFDR vs. Supply SINAD vs. Supply Figure 29. Figure 30.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 31. Figure 32. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 33. Figure 34. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 35. Figure 36.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 14 SFDR vs. Temperature SINAD vs. Temperature Figure 37. Figure 38. ENOB vs. Supply ENOB vs. Clock Frequency Figure 39. Figure 40. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 41. Figure 42.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 43. Figure 44. Spectral Response - 5V, 200 ksps Power Consumption vs. Throughput Figure 45. Figure 46.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC102S021 OPERATION The ADC102S021 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC102S021 in both track and hold modes are shown in Figure 47 and Figure 48, respectively.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting at the 5th clock.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com 111...111 ADC CODE 111...110 111...000 | | 1LSB = VA/1024 011...111 000...010 | 000...001 000...000 0V +VA - 1.5LSB 0.5LSB ANALOG INPUT Figure 49. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC102S021 is shown in Figure 50.
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ADC102S021 www.ti.com SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 VA D1 R1 C2 30 pF VIN C1 3 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 51. Equivalent Input Circuit DIGITAL INPUTS AND OUTPUTS The ADC102S021's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latchup risk.
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ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision F (March 2013) to Revision G • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC102S021CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC102S021CIMMX/NOP VSSOP B DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC102S021CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.
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