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ADC10662, ADC10664

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SNAS076E –JUNE 1999–REVISED MARCH 2013

ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold

Check for Samples: ADC10662, ADC10664

FEATURES

DESCRIPTION

NOTE: The ADC10662 is obsolete. It is described

• Built-In Sample-and-Hold

here for reference only.

• Single +5V Supply

Using an innovative, patented multistep (U.S. Patent

• No External Clock Required

Number 4918449) conversion technique, these 10-bit

• Speed Adjust Pin for Faster Conversions

CMOS analog-to-digital converters offer sub-

microsecond conversion times yet dissipating a

APPLICATIONS

maximum of only 235 mW. These converters perform

10-bit conversions in two lower-resolution “flashes”,

• Digital Signal Processor Front Ends

yielding a fast A/D without the cost, power

• Instrumentation

consumption, and other problems associated with

• Disk Drives

true flash approaches. In addition to standard static

performance specifications (Linearity, Full-Scale

• Mobile Telecommunications

Error, etc.), dynamic performance (THD, S/N) is

ensured.

KEY SPECIFICATIONS

The analog input voltage ADC is sampled and held

• Conversion Time 360 ns (Typical)

by an internal sampling circuit. Input signals at

• Max. Sampling Rate: 1.5 MHz (Min)

frequencies from DC to over 250 kHz can therefore

• Low Power Consumption 235 mW (Max)

be digitized accurately without the need for an

external sample-and-hold circuit.

• Total Harmonic Distortion (50 kHz): −60 dB

(Max)

Connecting an external resistor between the “speed-

up” pin and ground reduces the typical conversion

• No Missing Codes Over Temperature

time to as little as 360 ns for a small linearity

sacrifice.

For ease of interface to microprocessors, the

ADC10662 and ADC10664 have been designed to

appear as a memory location or I/O port without the

need for external interface logic.

Simplified Block Diagram

*ADC10664 Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold Check for Samples: ADC10662, ADC10664 FEATURES DESCRIPTION • • • • NOTE: The ADC10662 is obsolete. It is described here for reference only. 1 2 Built-In Sample-and-Hold Single +5V Supply No External Clock Required Speed Adjust Pin for Faster Conversions KEY SPECIFICATIONS Using an innovative, patented multistep (U.S.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. Top View Figure 2. Top View NOTE: The ADC10662 is obsolete; shown for reference only. PIN DESCRIPTIONS Pin Function Description DVCC, AVCC Digital and analog positive supply voltage inputs. Connect both to the same voltage source, but bypass separately with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to ground at each pin. INT Active low interrupt output.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Supply Voltage (V+ = AVCC = DVCC) −0.3V to +6V −0.3V to V+ + 0.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Converter Characteristics The following specifications apply for V+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjust pin connected to ground through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for TA = TJ = TMin to TMax; all other limits TA = TJ = +25°C. Symbol Parameter Typical (1) Conditions Resolution Integral Linearity Error ±0.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 DC Electrical Characteristics The following specifications apply for V+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjust pin connected to ground through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol VIN(1) Parameter Conditions Typical (1) V+ = 5.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 Timing Diagrams The conversion time (tCONV) is set by the internal timer. Figure 3. Mode 1 The conversion time (tCRD) includes the sampling time and is determined by the internal timer. Figure 4.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 8 Zero (Offset) Error vs. Reference Voltage Linearity Error vs. Reference Voltage Figure 5. Figure 6. Analog Supply Current vs. Temperature Digital Supply Current vs. Temperature Figure 7. Figure 8. Conversion Time vs. Temperature Conversion Time vs. Temperature Figure 9. Figure 10.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Conversion Time vs. Speed-Up Resistor Conversion Time vs. Speed-Up Resistor Figure 11. Figure 12. Spectral Response with 100 kHz Sine Wave Input Spectral Response with 100 kHz Sine Wave Input Figure 13. Figure 14. Signal-to-Noise + THD Ratio vs. Signal Frequency Linearity Change vs. Speed-Up Resistor Figure 15. Figure 16.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 10 Linearity Change vs. Speed-Up Resistor Linearity Error Change vs. Sample Time Figure 17. Figure 18.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC10662 is obsolete. It is discussed here for reference only. The ADC10662 and ADC10664 digitize an analog input signal to 10 bits accuracy by performing two lowerresolution “flash” conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the second flash conversion provides the four least significant bits LSBs).
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Figure 19. Block Diagram of the Multistep Converter Architecture SIMILAR PRODUCT DIFFERENCES The ADC1006x, ADC1046x and ADC1066x (where "x" indicates the number of multiplexer inputs) are similar devices with different specification limits. The differences in these device families are summarized below. Device Family ILE, TUE, PSS THD, SNR, ENOB Max.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 Table 1. Input Multiplexer Programming ADC10664 S1 S0 Channel 0 0 VIN0 0 1 VIN1 1 0 VIN2 1 1 VIN3 Table 2. Input Multiplexer Programming ADC10662 S0 Channel 0 VIN0 1 VIN1 Mode 2 In Mode 2, also called “RD mode”, the S/H and RD pins are tied together. A conversion is initiated by pulling both pins low. The A/D converter samples the input voltage and causes the coarse comparators to become active.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Correct conversion results will be obtained for input voltages greater than GND − 50 mV and less than V+ + 50 mV. Do not allow the signal source to drive the analog input pin beyond the Absolute Maximum Rating. If an analog input pin is forced beyond these voltages, the current flowing through the pin should be limited to 5 mA or less to avoid permanent damage to the IC.
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ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 LAYOUT AND GROUNDING In order to ensure fast, accurate conversions from the ADC10662 and ADC10664, it is necessary to use appropriate circuit board layout techniques. The analog ground return path should be low-impedance and free of noise from other parts of the system. Noise from digital circuitry can be especially troublesome.
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ADC10662, ADC10664 SNAS076E – JUNE 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 16 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC10664CIWMX/NOPB Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.4 3.2 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10664CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.
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