Datasheet

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ADC10731, ADC10732, ADC10734, ADC10738

www.ti.com

SNAS081D –MAY 1999–REVISED MARCH 2013

ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters

with Mux, Sample/Hold and Reference

Check for Samples: ADC10731, ADC10732, ADC10734, ADC10738

FEATURES

DESCRIPTION

The ADC10731, ADC10732 and ADC10734 are

• 0V to Analog Supply Input Range

obsolete or on lifetime buy and included for

• Serial I/O (MICROWIRE Compatible)

reference only.

• Software or Hardware Power Down

This series of CMOS 10-bit plus sign successive

• Analog Input Sample/Hold Function

approximation A/D converters features versatile

• Ratiometric or Absolute Voltage Referencing

analog input multiplexers, sample/hold and a 2.5V

band-gap reference. The 1-, 2-, 4-, or 8-channel

• No Zero or Full Scale Adjustment Required

multiplexers can be software configured for single-

• No Missing Codes Over Temperature

ended or differential mode of operation.

• TTL/CMOS Input/Output Compatible

An input sample/hold is implemented by a capacitive

reference ladder and sampled-data comparator. This

APPLICATIONS

allows the analog input to vary during the A/D

• Medical Instruments

conversion cycle.

• Portable and Remote Instrumentation

In the differential mode, valid outputs are obtained

even when the negative inputs are greater than the

• Test Equipment

positive because of the 10-bit plus sign output data

format.

KEY SPECIFICATIONS

The serial I/O is configured to comply with the

• Resolution 10 Bits Plus Sign

MICROWIRE serial data exchange standard for easy

• Single Supply 5 V

interface to the COPS and HPC families of

• Power Consumption 37 mW (Max)

controllers, and can easily interface with standard

shift registers and microprocessors.

• In Power Down Mode 18 μW

• Conversion Time 5 μs (Max)

• Sampling Rate 74 kHz (Max)

• Band-Gap Reference 2.5V ±2% (Max)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference Check for Samples: ADC10731, ADC10732, ADC10734, ADC10738 FEATURES DESCRIPTION • • • • • • • • The ADC10731, ADC10732 and ADC10734 are obsolete or on lifetime buy and included for reference only.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com ADC10738 Simplified Block Diagram Connection Diagrams The ADC10731, ADC10732 and ADC10734 are obsolete in all packages. They are in this data sheet for reference only. Top View Figure 1. ADC10731 16-Pin SOIC Package See Package Number DW0016B 2 Submit Documentation Feedback Top View Figure 2.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Top View Top View Figure 3. ADC10732 20-Pin SOIC Package See Package Number DW0020B Figure 4. ADC10738 24-Pin SOIC Package See Package Number DW0024B Figure 5. SSOP Package See Package Number DB0020A Table 1.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Table 1. Pin Descriptions (continued) Pin Name Description COM This pin is another analog input pin. It can be used as a “pseudo ground” when the analog multiplexer is single-ended. VREF+ This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range VREF (VREF = VREF+–VREF−) is 0.5 VDCto 5.0 VDC and the voltage at VREF+ cannot exceed AV+ +50 mV.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 7. Transfer Characteristics Figure 8.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Test Circuit Figure 9.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Typical Performance Characteristics Analog Supply Current (IA+) vs. Temperature Analog Supply Current (IA+) vs. Clock Frequency Figure 10. Figure 11. Digital Supply Current (ID+) vs. Temperature Digital Supply Current (ID+) vs. Clock Frequency Figure 12. Figure 13. Offset Error vs. Reference Voltage Offset Error vs. Temperature Figure 14. Figure 15.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 12 Linearity Error vs. Clock Frequency Linearity Error vs. Reference Voltage Figure 16. Figure 17. Linearity Error vs. Temperature 10-Bit Unsigned Signal-to-Noise + THD Ratio vs. Input Signal Level Figure 18. Figure 19. Spectral Response with 34 kHz Sine Wave Power Bandwidth Response with 380 kHz Sine Wave Figure 20. Figure 21.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Typical Reference Performance Characteristics Load Regulation Line Regulation Figure 22. Figure 23. Output Drift vs. Temperature (3 Typical Parts) Available Output Current vs. Supply Voltage Figure 24. Figure 25.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com TRI-STATE TEST CIRCUITS AND WAVEFORMS Figure 26. Figure 27. Figure 28. Figure 29. Timing Diagrams Figure 30.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 31. DO Timing Figure 32. Delayed DO Timing Figure 33.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Figure 34. Software Power Up/Down Sequence Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is invalid. The ADC10731 is obsolete. Information shown for reference only. Figure 35.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. Figure 36.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. Figure 38.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Table 2.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS The ADC10731, ADC10732 and ADC10734 are obsolete and discussed here for reference only. The ADC10731/2/4/8 use successive approximation to digitize an analog input voltage. The DAC portion of the A/D converters uses a capacitive array and a resistive ladder structure. The structure of the DAC allows a very simple switching scheme to provide a versatile analog input multiplexer.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 39. Detailed Diagram of the ADC10738 DAC and Analog Multiplexer Stages APPLICATIONS INFORMATION Multiplexer Configuration The design of these converters utilizes a sampled-data comparator structure, which allows a differential analog input to be converted by the successive approximation routine.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com The internal 2.5V bandgap reference in the ADC10731/2/4/8 is available as an output on the VREFOut pin. To ensure optimum performance this output needs to be bypassed to ground with 100 μF aluminum electrolytic or tantalum capacitor. The reference output can be unstable with capacitive loads greater than 100 pF and less than 100 μF.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Analog Input Multiplexer Options 4 Single-Ended 2 Differential 4 Psuedo-Differential 2 Single-Ended and 1 Differential Different Reference Configurations Figure 40.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Figure 41. Absolute Using a 4.096V Span Optional Adjustments Zero Error The zero error of the A/D converter relates to the location of the first riser of the transfer function (see Figure 7 Figure 8) and can be measured by grounding the minus input and applying a small magnitude voltage to the plus input.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 The Input Sample and Hold The ADC10731/2/4/8's sample/hold capacitor is implemented in the capacitor array. After the channel address is loaded, the array is switched to sample the selected positive analog input. The sampling period for the assigned positive input is maintained for the duration of the acquisition time (tA) 4.5 clock cycles. This acquisition window of 4.
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ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com *1% resistors Figure 44. Zero-Shift and Span-Adjust for Signed or Unsigned, Single-Ended Multiplexer Assignment, Signed Analog Input Range of 0.5V ≤ VIN ≤ 4.
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ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC10738CIWMX SOIC DW 24 1000 330.0 24.4 10.8 15.9 3.2 12.0 24.0 Q1 ADC10738CIWMX/NOPB SOIC DW 24 1000 330.0 24.4 10.8 15.9 3.2 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10738CIWMX SOIC DW 24 1000 367.0 367.0 45.0 ADC10738CIWMX/NOPB SOIC DW 24 1000 367.0 367.0 45.
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