Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply TSSOP 16

8 9

CS SCLK

DOUT

AGND DIN

IN0 V

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC108S022

www.ti.com

SNAS338F –SEPTEMBER 2005–REVISED MARCH 2013

ADC108S022 8-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

Check for Samples: ADC108S022

FEATURES

DESCRIPTION

The ADC108S022 is a low-power, eight-channel

• Eight Input Channels

CMOS 10-bit analog-to-digital converter specified for

• Variable Power Management

conversion throughput rates of 50 ksps to 200 ksps.

• Independent Analog and Digital Supplies

The converter is based on a successive-

approximation register architecture with an internal

• SPI/QSPI/MICROWIRE/DSP compatible

track-and-hold circuit. It can be configured to accept

• Packaged in 16-Lead TSSOP

up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is

APPLICATIONS

compatible with several standards, such as SPI,

• Automotive Navigation

QSPI, MICROWIRE, and many common DSP serial

• Portable Systems

interfaces.

• Medical Instruments

The ADC108S022 may be operated with independent

• Mobile Communications

analog and digital supplies. The analog supply (V

)

can range from +2.7V to +5.25V, and the digital

• Instrumentation and Control Systems

supply (V

) can range from +2.7V to V

. Normal

power consumption using a +3V or +5V supply is 1.1

KEY SPECIFICATIONS

mW and 6.4 mW, respectively. The power-down

• Conversion Rate 50 ksps to 200 ksps

feature reduces the power consumption to 0.09 µW

using a +3V supply and 0.3 µW using a +5V supply.

• DNL (V

= V

= 2.7V to 5.25V) ±0.3 LSB (max)

The ADC108S022 is packaged in a 16-lead TSSOP

• INL (V

= V

= 2.7V to 5.25V) ±0.3 LSB (max)

package. Operation over the extended industrial

• Power Consumption

temperature range of −40°C to +105°C is ensured.

– 3V Supply 1.1 mW (typ)

– 5V Supply 6.4 mW (typ)

Connection Diagram

Figure 1. Package Number PW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S022 8-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter Check for Samples: ADC108S022 FEATURES DESCRIPTION • • • • • The ADC108S022 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 50 ksps to 200 ksps. The converter is based on a successiveapproximation register architecture with an internal track-and-hold circuit.
PAGE 2
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Block Diagram IN0 . . . T/H MUX 10-BIT SUCCESSIVE APPROXIMATION ADC VA AGND AGND IN7 VD SCLK ADC108S022 CS CONTROL LOGIC DIN DOUT DGND PIN DESCRIPTIONS Pin No. Symbol Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF. DIGITAL I/O 16 SCLK Digital clock input. The ensured performance range of frequencies for this input is 0.8 MHz to 3.2 MHz.
PAGE 3
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to VA + 0.3V, max 6.5V Voltage on Any Pin to GND −0.3V to VA +0.3V (3) ±10 mA Input Current at Any Pin Package Input Current (3) ±20 mA (4) Power Dissipation at TA = 25°C See ESD Susceptibility (5) Human Body Model Machine Model 2500V 250V For soldering specifications: see www.ti.
PAGE 4
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S022 Converter Electrical Characteristics (1) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
PAGE 5
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S022 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
PAGE 6
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S022 Timing Specifications (continued) The following specifications apply for VA = VD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions CS Rising Edge to DOUT HighImpedance tDIS Limits Typical (1) Units DOUT falling 2.4 20 ns (max) DOUT rising 0.
PAGE 7
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Specification Definitions ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold capacitor is charged by the input voltage. APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion.
PAGE 8
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, including harmonics but excluding d.c.
PAGE 9
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 3.2 MHz, fIN = 40.2 kHz unless otherwise stated. DNL DNL Figure 5. Figure 6. INL INL Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
PAGE 10
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 3.2 MHz, fIN = 40.2 kHz unless otherwise stated. 10 SNR vs. Supply THD vs. Supply Figure 11. Figure 12. ENOB vs. Supply DNL vs. VD with VA = 5.0 V Figure 13. Figure 14. INL vs. VD with VA = 5.0 V DNL vs. SCLK Duty Cycle Figure 15. Figure 16.
PAGE 11
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 3.2 MHz, fIN = 40.2 kHz unless otherwise stated. INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle Figure 17. Figure 18. THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle Figure 19. Figure 20. DNL vs. SCLK INL vs. SCLK Figure 21. Figure 22.
PAGE 12
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 3.2 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. SCLK THD vs. SCLK Figure 23. Figure 24. ENOB vs. SCLK DNL vs. Temperature Figure 25. Figure 26. INL vs. Temperature SNR vs. Temperature Figure 27. Figure 28.
PAGE 13
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 3.2 MHz, fIN = 40.2 kHz unless otherwise stated. THD vs. Temperature ENOB vs. Temperature Figure 29. Figure 30. SNR vs. Input Frequency THD vs. Input Frequency Figure 31. Figure 32. ENOB vs. Input Frequency Power Consumption vs. SCLK Figure 33. Figure 34.
PAGE 14
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC108S022 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. ADC108S022 Operation Simplified schematics of the ADC108S022 in both track and hold operation are shown in Figure 35 and Figure 36 respectively.
PAGE 15
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros, falling edges 5 through 14 clock out the conversion result, MSB first, and falling edges 15 and 16 clock out trailing zeros.
PAGE 16
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com 111...111 111...000 | | ADC CODE 111...110 1 LSB = VA / 1024 011...111 000...010 | 000...001 000...000 0V 0.5LSB ANALOG INPUT +VA - 1.5LSB Figure 37. Ideal Transfer Characteristic Analog Inputs An equivalent circuit for one of the ADC108S022's input channels is shown in Figure 38. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0V to VA.
PAGE 17
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 Applications Information Typical Application Circuit A typical application is shown in Figure 39. The split analog and digital supply pins are both powered in this example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC108S022. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors.
PAGE 18
ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com PC = tN tN + tS u PN + tS tN + tS u PS Figure 40. Power Consumption Equation Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC.
PAGE 19
ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC108S022CIMTX/NOP B Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device ADC108S022CIMTX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 367.0 367.0 35.
PAGE 23
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.