Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply TSSOP 16

8 9

CS SCLK

DOUT

AGND DIN

IN0 V

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC108S052

www.ti.com

SNAS337G –SEPTEMBER 2005–REVISED MARCH 2013

ADC108S052 8-Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter

Check for Samples: ADC108S052

FEATURES

DESCRIPTION

The ADC108S052 is a low-power, eight-channel

• Eight Input Channels

CMOS 10-bit analog-to-digital converter specified for

• Variable Power Management

conversion throughput rates of 200 ksps to 500 ksps.

• Independent Analog and Digital Supplies

The converter is based on a successive-

approximation register architecture with an internal

• SPI™/ QSPI™/MICROWIRE/DSP Compatible

track-and-hold circuit. It can be configured to accept

• Packaged in 16-Lead TSSOP

up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is

KEY SPECIFICATIONS

compatible with several standards, such as SPI™,

• Conversion Rate: 200 ksps to 500 ksps

QSPI™, MICROWIRE, and many common DSP

• DNL (V

= V

= 2.7V to 5.0V): ±0.4 LSB (max)

serial interfaces.

• INL (VA = VD = 2.7V to 5.0V): ±0.4 LSB (max)

The ADC108S052 may be operated with independent

• Power Consumption:

analog and digital supplies. The analog supply (V

)

can range from +2.7V to +5.25V, and the digital

– 3V Supply: 1.5 mW (typ)

supply (V

) can range from +2.7V to V

. Normal

– 5V Supply: 7.5 mW (typ)

power consumption using a +3V or +5V supply is 1.5

mW and 7.5 mW, respectively. The power-down

APPLICATIONS

feature reduces the power consumption to 0.09 µW

using a +3V supply and 0.30 µW using a +5V supply.

• Automotive Navigation

The ADC108S052 is packaged in a 16-lead TSSOP

• Portable Systems

package. Operation over the extended industrial

• Medical Instruments

temperature range of −40°C to +105°C is ensured.

• Mobile Communications

• Instrumentation and Control Systems

Connection Diagram

Figure 1. TSSOP Package

See Package Number PW0016A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S052 8-Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter Check for Samples: ADC108S052 FEATURES DESCRIPTION • • • • • The ADC108S052 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 200 ksps to 500 ksps. The converter is based on a successiveapproximation register architecture with an internal track-and-hold circuit.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Block Diagram IN0 . . . T/H MUX 10-BIT SUCCESSIVE APPROXIMATION ADC VA AGND AGND IN7 VD SCLK ADC108S052 CONTROL LOGIC CS DIN DOUT DGND Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF. DIGITAL I/O 16 SCLK Digital clock input. The specified performance range of frequencies for this input is 3.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to VA + 0.3V, max 6.5V −0.3V to VA +0.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S052 Converter Electrical Characteristics (1) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S052 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S052 Timing Specifications The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 Timing Diagrams Power Down Power Up Track Power Up Hold Track Hold CS 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 SCLK Control register DIN ADD2 DOUT ADD1 ADD0 ADD2 DB9 FOUR ZEROS DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADD1 ADD0 DB9 SIX ZEROS DB8 DB7 Figure 2.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Specification Definitions ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold capacitor is charged by the input voltage. APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, including harmonics but excluding d.c.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics TA = +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL DNL Figure 5. Figure 6. INL INL Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Supply THD vs. Supply Figure 11. Figure 12. ENOB vs. Supply DNL vs. VD with VA = 5.0 V Figure 13. Figure 14. INL vs. VD with VA = 5.0 V DNL vs. SCLK Duty Cycle Figure 15. Figure 16.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle Figure 17. Figure 18. THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle Figure 19. Figure 20. DNL vs. SCLK INL vs. SCLK Figure . Figure 21.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. SCLK THD vs. SCLK Figure . Figure 22. ENOB vs. SCLK DNL vs. Temperature Figure 23. Figure 24. INL vs. Temperature SNR vs. Temperature Figure 25. Figure 26.
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 THD vs. Temperature ENOB vs. Temperature Figure 27. Figure 28. SNR vs. Input Frequency THD vs. Input Frequency Figure 29. Figure 30. ENOB vs. Input Frequency Power Consumption vs. SCLK Figure 31. Figure 32.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC108S052 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. ADC108S052 OPERATION Simplified schematics of the ADC108S052 in both track and hold operation are shown in Figure 33 and Figure 34 respectively.
PAGE 16
ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com SERIAL INTERFACE An operational timing diagram and a serial interface timing diagram for the ADC108S052 are shown in The Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first.
PAGE 17
ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S052 TRANSFER FUNCTION The output format of the ADC108S052 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC108S052 is VA / 1024. The ideal transfer characteristic is shown in Figure 35. The transition from an output code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a voltage of VA / 2048. Other code transitions occur at steps of one LSB. 111...
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ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com DIGITAL INPUTS AND OUTPUTS The ADC108S052's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT) operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is 0.4V (max).
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 POWER SUPPLY CONSIDERATIONS There are three major power supply concerns with this product: power supply sequencing, power management, and the effect of digital supply noise on the analog supply. Power Supply Sequence The ADC108S052 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised to ensure that the power is applied in the correct sequence.
PAGE 20
ADC108S052 SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com LAYOUT AND GROUNDING Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance.
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ADC108S052 www.ti.com SNAS337G – SEPTEMBER 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC108S052CIMTX/NOP B Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device ADC108S052CIMTX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 367.0 367.0 35.
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