Datasheet

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ADC1173

www.ti.com

SNAS025F –FEBRUARY 1999–REVISED APRIL 2013

ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter

Check for Samples: ADC1173

FEATURES

DESCRIPTION

The ADC1173 is a low power, 15 MSPS analog-to-

• Internal Sample-and-Hold Function

digital converter that digitizes signals to 8 bits while

• Single +3V Operation

consuming just 33 mW of power (typ). The ADC1173

• Internal Reference Bias Resistors

uses a unique architecture that achieves 7.6 Effective

Bits. Output formatting is straight binary coding.

• Industry Standard Pinout

The excellent DC and AC characteristics of this

APPLICATIONS

device, together with its low power consumption and

+3V single supply operation, make it ideally suited for

• Video Digitization

many video, imaging and communications

• Digital Still Cameras

applications, including use in portable equipment.

• Set Top Boxes

Furthermore, the ADC1173 is resistant to latch-up

and the outputs are short-circuit proof. The top and

• Camcorders

bottom of the ADC1173's reference ladder is

• Personal Computer Video

available for connections, enabling a wide range of

• Digital Television

input possibilities.

• CCD Imaging

The ADC1173 is offered in a 24-pin TSSOP package

• Electro-Optics

and is designed to operate over the -40°C to +75°C

commercial temperature range.

KEY SPECIFICATIONS

PIN CONFIGURATION

• Resolution 8 Bits

• Maximum Sampling Frequency 15 MSPS (min)

• THD −54 dB (typ)

• DNL ±0.85 LSB (max)

• ENOB at 3.58 MHz Input 7.6 Bits (typ)

• Differential Phase 0.5 Degree (max)

• Differential Gain 1.5% (typ)

• Power Consumption 33 mW (typ) (excluding

reference current)

Figure 1. 24-Pin TSSOP (Top View)

See PW Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter Check for Samples: ADC1173 FEATURES DESCRIPTION • • • • The ADC1173 is a low power, 15 MSPS analog-todigital converter that digitizes signals to 8 bits while consuming just 33 mW of power (typ). The ADC1173 uses a unique architecture that achieves 7.6 Effective Bits. Output formatting is straight binary coding.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit Description 19 VIN Analog signal input. Conversion range is VRB to VRT. 16 VRTS Reference Top Bias with internal pull-up resistor. Short this pin to VRT to self bias the reference ladder. 17 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AVDD.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description 1 OE CMOS/TTL compatible Digital input that, when low, enables the digital outputs of the ADC1173. When high, the outputs are in a high impedance state. 12 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. 3 thru 10 D0-D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) AVDD, DVDD 6.5V −0.3V to 6.5V Voltage on Any Pin VRT, VRB AVDD to VSS −0.5 to (AVDD + 0.5V) CLK, OE Voltage Digital Output Voltage Input Current DVSS to DVDD (4) ±25mA Package Input Current (4) ±50mA Package Dissipation at 25°C ESD Susceptibility (6) See Human Body Model 2000V Machine Model 200V Soldering Temp., Infrared, 10 sec.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply for AVDD = DVDD = +3.0VDC, OE = 0V, VRT = +2.0V, VRB = 0V, CL = 20 pF, fCLK = 15MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2) Symbol Parameter Conditions Typical (3) Limits Units DC Accuracy INL Integral Non Linearity ±0.5 ±1.3 LSB ( max) DNL Differential Non Linearity ±0.4 ±0.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +3.0VDC, OE = 0V, VRT = +2.0V, VRB = 0V, CL = 20 pF, fCLK = 15MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2) Symbol Parameter VRTS VRBS Self Bias Voltage Delta VRT - VRB Reference Voltage Delta Conditions Typical VRT connected to VRTS, VRB connected to VRBS 1.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +3.0VDC, OE = 0V, VRT = +2.0V, VRB = 0V, CL = 20 pF, fCLK = 15MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2) Symbol THD 8 Parameter Total Harmonic Distortion Conditions fIN = 1.31 MHz fIN = 3.58 MHz fIN = 7.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS INL vs. Temperature DNL vs. Temperature Figure 2. Figure 3. SNR vs. Temperature SNR vs. fIN Figure 4. Figure 5. THD vs. Temperature SINAD vs. Temperature Figure 6. Figure 7.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 SINAD vs. fIN SFDR vs. Temperature Figure 8. Figure 9. SFDR vs. fIN Differential Gain vs. Temperature Figure 10. Figure 11. Differential Phase vs. Temperature SNR vs. fIN Figure 12. Figure 13.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD vs. fIN SINAD vs. fIN Figure 14. Figure 15. SFDR vs. fIN SNR vs. SUPPLY VOLTAGE Figure 16. Figure 17. THD vs. SUPPLY VOLTAGE SINAD vs. SUPPLY VOLTAGE Figure 18. Figure 19.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 12 SFDR vs. SUPPLY VOLTAGE IDDD + IADD vs. fCLK Figure 20. Figure 21. TOD vs. Temperature Spectral Response Figure 22. Figure 23.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 SPECIFICATION DEFINITIONS ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com Timing Diagram Figure 24. Timing Diagram Figure 25.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC1173 uses a new, unique architecture to achieve 7.4 effective bits at and maintains superior dynamic performance up to ½ the clock frequency. The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 20 MSPS. Input voltages below VRB will cause the output word to consist of all zeroes.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION THE ANALOG INPUT The analog input of the ADC1173 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 Because of resistor tolerances, the reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text). Figure 26. Simple, Low Component Count, Self -Bias Reference application. The reference self-bias circuit of is very simple and performance is adequate for many applications. Superior performance can generally be achieved by driving the reference pins with a low impedance source.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com Self-bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. Figure 27. Better defining the ADC Reference Voltage.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 Driving the reference to force desired values requires driving with a low impedance source, provided by the transistors. Note that pins 16 and 22 are not connected. Figure 28. Driving with a low impedance source If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of will allow forcing the reference voltages to whatever levels are desired.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com As is the case with all high speed converters, the ADC1173 should be assumed to have little a.c. power supply rejection, especially when self-biasing is used by connecting VRT and VRTS together. No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing should be avoided as even a little coupling can cause problems at high frequencies.
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ADC1173 SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin.
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ADC1173 www.ti.com SNAS025F – FEBRUARY 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC1173CIMTCX/NOPB TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC1173CIMTCX/NOPB TSSOP PW 24 2500 367.0 367.0 35.
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