Datasheet

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ADC1175

www.ti.com

SNAS012H –JANUARY 2000–REVISED APRIL 2013

ADC1175 8-Bit, 20MHz, 60mW A/D Converter

Check for Samples: ADC1175

FEATURES

DESCRIPTION

The ADC1175 is a low power, 20 Msps analog-to-

• Internal Sample-and-Hold Function

digital converter that digitizes signals to 8 bits while

• Single +5V Operation

consuming just 60 mW of power (typ). The ADC1175

• Internal Reference Bias Resistors

uses a unique architecture that achieves 7.5 Effective

Bits. Output formatting is straight binary coding.

• Industry Standard Pinout

• TRI-STATE Outputs

The excellent DC and AC characteristics of this

device, together with its low power consumption and

+5V single supply operation, make it ideally suited for

APPLICATIONS

many video, imaging and communications

• Video Digitization

applications, including use in portable equipment.

• Digital Still Cameras

Furthermore, the ADC1175 is resistant to latch-up

and the outputs are short-circuit proof. The top and

• Personal Computer Video Cameras

bottom of the ADC1175's reference ladder is

• CCD Imaging

available for connections, enabling a wide range of

• Electro-Optics

input possibilities.

The ADC1175 is offered in a TSSOP. It is designed

KEY SPECIFICATIONS

to operate over the commercial temperature range of

• Resolution 8Bits

-20°C to +75°C.

• Maximum Sampling Frequency 20Msps (min)

• DNL 0.75 LSB (max)

• ENOB 7.5 Bits (typ)

• Ensured No Missing Codes

• Power Consumption (excluding I

REF

) 60mW

(typ)

PIN CONFIGURATION

ADC1175 Pin Configuration

TSSOP Package

See Package Number PW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 ADC1175 8-Bit, 20MHz, 60mW A/D Converter Check for Samples: ADC1175 FEATURES DESCRIPTION • • • • • The ADC1175 is a low power, 20 Msps analog-todigital converter that digitizes signals to 8 bits while consuming just 60 mW of power (typ). The ADC1175 uses a unique architecture that achieves 7.5 Effective Bits. Output formatting is straight binary coding.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM Figure 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. 2 Symbol 19 VIN 16 VRTS Equivalent Circuit Description Analog signal input. Conversion range is VRB to VRT. Reference Top Bias with internal pull-up resistor. Short this pin to VRT to self bias the reference ladder.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AVDD. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See REFERENCE INPUTS for more information. 23 VRB Analog Input that is the low (bottom) side of the reference ladder of the ADC.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description DVDD 12 CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. CLK 12 DVSS DVDD 3 thru 10 D0-D7 Dn Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are enabled by bringing the OE pin low.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) AVDD, DVDD 6.5V Voltage on Any Pin −0.3V to 6.5V VRT, VRB AVSS to AVDD −0.5 to (AVDD + 0.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2) Symbol Parameter Conditions Typical (3) Limits (3) Units ±1.3 LSB ( max) DC Accuracy INL Integral Non Linearity f CLK = 20 MHz ±0.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1)(2) Symbol Parameter Typical (3) Conditions Limits (3) Units Power Supply Characteristics IADD Analog Supply Current DVDD = AVDD =5.25V 9.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1)(2) Symbol SFDR THD Parameter Spurious Free Dynamic Range Total Harmonic Distortion Conditions Typical (3) fIN = 1.31 MHz, VIN = FS - 2 LSB 56 fIN = 4.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS INL vs. Temp at fCLK DNL vs. Temp at fCLK Figure 3. Figure 4. SNR vs. Temp at fCLK SNR vs. Temp at fCLK Figure 5. Figure 6. THD vs. Temp THD vs. Temp Figure 7. Figure 8.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 SINAD/ENOB vs. Temp SINAD/ENOB vs. Temp Figure 9. Figure 10. SINAD and ENOB vs. Clock Duty Cycle SFDR vs. Temp and fIN Figure 11. Figure 12. SFDR vs. Temp and fIN Differential Gain vs. Temperature Figure 13. Figure 14.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Differential Phase vs. Temperature Spectral Response at fCLK = 20 MSPS Figure 15. Figure 16.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com SPECIFICATION DEFINITIONS ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 TIMING DIAGRAM Figure 17. ADC1175 Timing Diagram Figure 18.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC1175 uses a new, unique architecture to achieve 7.2 effective bits at and maintains superior dynamic performance up to ½ the clock frequency. The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 30 MSPS. Input voltages below VRB will cause the output word to consist of all zeroes.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 APPLICATIONS INFORMATION THE ANALOG INPUT The analog input of the ADC1175 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load.
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ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com +5V Choke 150, 1% 0.1 PF 237, 1% 57.6, 1% 10 PF 237, 1% 2 Analog Input + + 10 PF 3 + 150 1% 6 110 14 15 18 11 13 AVDD 19 0.1 PF DVDD to AVDD 62 pF LMH6702 16 17 VRTS VRT 10 PF ADC1175 23 22 D7 D6 D5 D4 D3 D2 D1 D0 10 9 8 7 6 5 4 3 VRB VRBS 10 PF OE to AVSS AVSS 20 21 DVSS 2 24 1 CLK 12 Because of resistor tolerances, the reference voltages can vary by as much as 6%.
PAGE 17
ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 Self-bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. Figure 20.
PAGE 18
ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Driving the reference to force desired values requires driving with a low impedance source, provided by the transistors. Pins 16 and 22 are not connected. Figure 21. POWER SUPPLY CONSIDERATIONS Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins. Pins 11 and 13 are both labeled DVDD.
PAGE 20
ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing should be avoided as even a little coupling can cause problems at high frequencies.
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ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin.
PAGE 22
ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision G (April 2013) to Revision H • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC1175CIMTCX/NOPB TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC1175CIMTCX/NOPB TSSOP PW 24 2500 367.0 367.0 35.
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