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ADC12048

www.ti.com

SNAS105B –APRIL 2000–REVISED MARCH 2013

ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter

Check for Samples: ADC12048

FEATURES

DESCRIPTION

Operating from a single 5V power supply, the

• 8-Channel Programmable Differential or

ADC12048 is a 12 bit + sign, parallel I/O, self-

Single-Ended Multiplexer

calibrating, sampling analog-to-digital converter

• Programmable Acquisition Times and User-

(ADC) with an eight input fully differential analog

Controllable Throughput Rates

multiplexer. The maximum sampling rate is 216 kHz.

On request, the ADC goes through a self-calibration

• Programmable Data Bus Width (8/13 bits)

process that adjusts linearity, zero and full-scale

• Built-in Sample-and-Hold

errors.

• Programmable Auto-Calibration and Auto-Zero

The ADC12048's 8-channel multiplexer is software

cycles

programmable to operate in a variety of combinations

• Low Power Standby Mode

of single-ended, differential, or pseudo-differential

• No Missing Codes

modes. The fully differential MUX and the 12-bit +

sign ADC allows for the difference between two

signals to be digitized.

APPLICATIONS

• Medical Instrumentation

The ADC12048 can be configured to work with many

popular microprocessors/microcontrollers and DSPs

• Process Control Systems

including Tl's HPC family, Intel386 and 8051,

• Test Equipment

TMS320C25, Motorola MC68HC11/16, Hitachi 64180

• Data Logging

and Analog Devices ADSP21xx.

• Inertial Guidance

For complementary voltage references see the

LM4040, LM4041 or LM9140.

KEY SPECIFICATIONS

• (f

CLK

= 12 MHz)

• Resolution: 12-Bits + Sign

• 13-Bit Conversion Time: 3.6 μs, Max

• 13-Bit Throughput Rate: 216 ksamples/s, Min

• Integral Linearity Error (ILE): ±1 LSB, Max

• Single Supply: +5 V ±10%

• V

Range: GND to V

• Power Consumption

– Normal Operation: 34 mW, Max

– Stand-By Mode: 75 μw, Max

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter Check for Samples: ADC12048 FEATURES DESCRIPTION • Operating from a single 5V power supply, the ADC12048 is a 12 bit + sign, parallel I/O, selfcalibrating, sampling analog-to-digital converter (ADC) with an eight input fully differential analog multiplexer. The maximum sampling rate is 216 kHz.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Block Diagram Connection Diagrams Figure 1. PLCC Package See Package Number FN0044A 2 Figure 2.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 PIN DESCRIPTION PLCC Pkg. Pin Number PQFP Pkg. Pin Number Pin Name Description 6 44 CH0 7 1 CH1 The eight analog inputs to the Multiplexer. Active channels are selected based on the contents of bits b3–b0 of the Configuration register. Refer to INPUT MULTIPLEXER for more details.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTION (continued) PLCC Pkg. Pin Number PQFP Pkg. Pin Number Pin Name Description 10 4 VA+ Analog supply input pin. The device operating supply voltage range is +5V ±10%. Accuracy is ensured only if the VA+ and VD+ are connected to the same potential. This pin should be bypassed to AGND with a parallel combination of a 10 μF and a 0.1 μF (ceramic) capacitor.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Operating Ratings (1) (2) (3) (4) (5) (6) Temperature Range (Tmin ≤ TA ≤ Tmax) Supply Voltage VA+, VD+ −40°C ≤ TA ≤ 85°C 4.5V to 5.5V |VA+ − VD+| ≤100 mV |AGND − DGND| ≤100 mV GND ≤ VIN ≤ VA+ VIN Voltage Range at all Inputs VREF+ Input Voltage 1V ≤ VREF+ ≤ VA+ VREF− Input Voltage 0 ≤ VREF− ≤ VREF+ − 1V VREF+ − VREF− 1V ≤ VREF ≤ VA+ VREF Common Mode (7) (1) 0.1 VA+ ≤ VREFCM ≤ 0.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Power Supply Characteristics The following specifications apply to the ADC12048 for VA+ = VD+ = 5V, VREF+ = 4.096V, VREF− = 0.0V, 12-bit + sign conversion mode, fCLK = 12.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 1Ω, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Reference Inputs The following specifications apply to the ADC12048 for VA+ = VD+ = 5V, VREF+ = 4.096V, VREF− = 0.0V, 12-bit + sign conversion mode, fCLK = 12.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 1Ω, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Figure 4. Electrical Characteristics Figure 5. Output Digital Code vs the Operating Input Voltage Range (General Case) Figure 6. Output Digital Code vs the Operating Input Voltage Range for VREF = 4.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 7. VREF Operating Range (General Case) Figure 8.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Figure 9. Transfer Characteristic Figure 10. Simplified Error vs Output Code without Auto-Calibration or Auto-Zero Cycles Figure 11.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 12. Offset or Zero Error Voltage (3) Timing Diagrams Figure 13. Sync-Out Write (WMODE = 1, BW = 1), Read and Convert Cycles (3) 12 Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions between −1 to 0 and 0 to +1 (see Figure 12).
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Figure 14. Sync-In Write (WMODE = 1, BW = 1), Read and Convert Cycles Figure 15.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 16. Sync-In Write (WMODE = 0, BW = 1), Read and Convert Cycles The MUX channel is the channel selected on the most recent write cycle. Figure 17. Sync-Out Read and Convert Cycles.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 The MUX channel is the channel selected on the most recent write cycle. Figure 18. Sync-In Read and Convert Cycles. Figure 19.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 20. 8-Bit Bus Read Cycle (Sync-In) Figure 21.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Figure 22.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics See Figure 4 (1) (1) 18 Integral Linearity Error (INL) Change vs. Clock Frequency Full-Scale Error Change vs. Clock Frequency Figure 23. Figure 24. Zero Error Change vs. Clock Frequency Integral Linearity Error (INL) Change vs. Temperature Figure 25. Figure 26. Full-Scale Error Change vs. Temperature Zero Error Change vs. Temperature Figure 27. Figure 28.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) (1) See Figure 4 Integral Linearity Error (INL) Change vs. Reference Voltage Full-Scale Error Change vs. Reference Voltage Figure 29. Figure 30. Zero Error Change vs. Reference Voltage Integral Linearity Error (INL) Change vs. Supply Voltage Figure 31. Figure 32. Full-Scale Error Change vs. Supply Voltage Zero Error Change vs. Supply Voltage Figure 33. Figure 34.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics See Figure 4 (1) (1) 20 Supply Currents vs. Clock Frequency Reference Currents vs. Clock Frequency Figure 35. Figure 36. Analog Supply Current vs. Temperature Digital Supply Current vs. Temperature Figure 37. Figure 38. Full Scale Differential 1,099 Hz Sine Wave Input Full Scale Differential 18,677 Hz Sine Wave Input Figure 39. Figure 40.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) (1) See Figure 4 Full Scale Differential 38,452 Hz Sine Wave Input Full Scale Differential 79,468 Hz Sine Wave Input Figure 41. Figure 42. Half Scale Differential 1 kHz Sine Wave Input, fS = 153.6 kHz Half Scale Differential 20 kHz Sine Wave Input, fS = 153.6 kHz Figure 43. Figure 44. Half Scale Differential 40 kHz Sine Wave Input, fS = 153.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com REGISTER BIT DESCRIPTION CONFIGURATION REGISTER (Write Only) This is a 13-bit write-only register that is used to program the functionality of the ADC12048. All data written to the ADC12048 will always go to this register only. The contents of this register cannot be read.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 b8: The SYNC bit. When the SYNC bit is set, the SYNC pin is programmed as an input and the converter is in synchronous mode. In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and begin a conversion. When b15 cleared, the SYNC pin is programmed as an output and the converter is in an asynchronous mode. In this mode the signal at the SYNC pin indicates the status of the converter.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com In 8-bit mode the Configuration register is byte accessible. The HB bit in the lower byte of the Configuration register is used to access the upper byte. If the HB bit is set with a write to the lower byte, the next byte written to the ADC will be placed in the upper byte of the Configuration register.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 SELECTABLE ACQUISITION TIME The ADC12048's internal sample/hold circuitry samples an input voltage by connecting the input to an internal sampling capacitor (approximately 70 pF) through an effective resistance equal to the multiplexer “On” resistance (300Ω max) plus the “On” resistance of the analog switch at the input to the sample/hold circuit (2500Ω typical) and the effective output resistance of the source.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com AUTO-ZERO CYCLE During an auto-zero cycle, the offset is measured only once and a correction coefficient is created and stored in an internal offset register. An auto-zero cycle is initiated by writing an Auto-Zero command to the ADC12048. DIGITAL INTERFACE The digital control signals are CS, RD, WR, RDY and STDBY. Specific timing relationships are associated with the interaction of these signals.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 acquisition time and operational command can be written into the configuration register or it can remain unchanged. With the START command in the Configuration register, a read from the ADC12048 will place the entire 13-bit conversion result stored in the data register on the data bus. The rising edge of the read pulse will immediately force the RDY output high.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com Analog Application Information REFERENCE VOLTAGE The ADC12048 has two reference inputs, VREF+ and VREF−. They define the zero to full-scale range of the analog input signals over which 4095 positive and 4096 negative codes exist. The reference inputs can be connected to span the entire supply voltage range (VREF− = AGND, VREF+ = VA+) or they can be connected to different voltages when other input spans are required.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Part Number Output Voltage Temperature Tolerance Coefficient LM4041CI-Adj ±0.5% ±100ppm/°C LM4040AI-4.1 ±0.1% ±100ppm/°C LM4050 ±0.2% ±50ppm/°C LM4121 ±0.1% ±50ppm/°C ±0.5% ±25ppm/°C LM9140BYZ-4.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com When the power supply regulator is not local on the board, adequate bypassing (a high value electrolytic capacitor) should be placed at the power entry point. The value of the capacitor depends on the total supply current of the circuits on the PC board. All supply currents should be supplied by the capacitor instead of being drawn from the external supply lines, while the external supply charges the capacitor at a steady rate.
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ADC12048 www.ti.com SNAS105B – APRIL 2000 – REVISED MARCH 2013 Figure 49. Top View of Printed Circuit Board for a 44-Pin PLCC ADC12048 When measuring AC input signals, any crosstalk between analog input/output lines and the reference lines (CH0–CH7, MUXOUT±, ADC IN±, VREF±) should be minimized. Crosstalk is minimized by reducing any stray capacitance between the lines.
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ADC12048 SNAS105B – APRIL 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B • 32 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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