Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply SOT 23 6

3 4

GND

SDATA

SCLK

ADC121S101

www.ti.com

SNAS304F –JANUARY 2006–REVISED MAY 2013

ADC121S101/ADC121S101–Q1 Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter

Check for Samples: ADC121S101

FEATURES

DESCRIPTION

The ADC121S101 is a low-power, single channel

• Specified Over a Range of Sample Rates

CMOS 12-bit analog-to-digital converter with a high-

• 6-lead WSON and SOT-23 Packages

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC121S101 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 500 ksps to 1 Msps. The

• SPI™/QSPI™/MICROWIRE/DSP Compatible

converter is based upon a successive-approximation

• AEC-Q100 Grade 1 Qualified

circuit.

APPLICATIONS

The output serial data is straight binary, and is

• Portable Systems

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

• Remote Data Acquisition

serial interfaces.

• Instrumentation and Control Systems

The ADC121S101 operates with a single supply that

• Automotive

can range from +2.7V to +5.25V. Normal power

consumption using a +3V or +5V supply is 2.0 mW

KEY SPECIFICATIONS

and 10 mW, respectively. The power-down feature

• DNL: +0.5 / −0.3 LSB (typ)

reduces the power consumption to as low as 2.6 µW

using a +5V supply.

• INL: ±0.40 LSB (typ)

The ADC121S101 is packaged in 6-lead WSON and

• Power Consumption

SOT-23 packages. Operation over the temperature

– 3V Supply: 2.0 mW(typ)

range of −40°C to +125 °C is specified.

– 5V Supply: 10 mW (typ)

PIN-COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC101S101

8-bit ADC081S021 ADC081S051 ADC081S101

(1) All devices are fully pin and function compatible.

CONNECTION DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 ADC121S101/ADC121S101–Q1 Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter Check for Samples: ADC121S101 FEATURES DESCRIPTION • • • • • • The ADC121S101 is a low-power, single channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S101 is fully specified over a sample rate range of 500 ksps to 1 Msps.
PAGE 2
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAM VIN T/H 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA PIN DESCRIPTIONS Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA.
PAGE 3
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to 6.5V Voltage on Any Digital Pin to GND −0.3V to (VA +0.
PAGE 4
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com ADC121S101 CONVERTER ELECTRICAL CHARACTERISTICS (1) (2) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40°C to +125°C: all other limits TA = 25°C unless otherwise noted.
PAGE 5
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 ADC121S101 CONVERTER ELECTRICAL CHARACTERISTICS(1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40°C to +125°C: all other limits TA = 25°C unless otherwise noted. Symbol Limits (2) Units VA = +5.25V 2.4 V (min) VA = +3.6V 2.1 V (min) VA = +5V 0.8 V (max) VA = +3V 0.
PAGE 6
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com ADC121S101 TIMING SPECIFICATIONS The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10.0 MHz to 20.0 MHz, CL = 25 pF, fSAMPLE = 500 ksps to 1 Msps, Boldface limits apply for TA = -40°C to +125°C; all other limits TA = 25°C.
PAGE 7
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 Hold Track | CS tCS tSU tACQ tCL 1 2 3 4 12 13 14 15 16 17 18 Z1 Z0 DB11 3 leading zero bits 19 20 tQUIET tCH tH | Z2 5 tACC tEN SDATA | SCLK tDIS TRI-STATE DB3 DB2 DB1 DB0 12 data bits Figure 2. ADC121S101 Serial Timing Diagram SPECIFICATION DEFINITIONS ACQUISITION TIME is the time required to acquire the input voltage.
PAGE 8
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs.
PAGE 9
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS TA = +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. DNL fSCLK = 10 MHz INL fSCLK = 10 MHz Figure 3. Figure 4. DNL fSCLK = 20 MHz INL fSCLK = 20 MHz Figure 5. Figure 6. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 7. Figure 8.
PAGE 10
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. 10 SNR vs. Clock Frequency SINAD vs. Clock Frequency Figure 9. Figure 10. SFDR vs. Clock Frequency THD vs. Clock Frequency Figure 11. Figure 12. Spectral Response, VA = 5.25V fSCLK = 10 MHz Spectral Response, VA = 5.25V fSCLK = 20 MHz Figure 13. Figure 14.
PAGE 11
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. Power Consumption vs. Throughput, fSCLK = 20 MHz Figure 15.
PAGE 12
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com APPLICATIONS INFORMATION ADC121S101 OPERATION The ADC121S101 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC121S101 in both track and hold modes are shown in Figure 16 and Figure 17, respectively.
PAGE 13
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by twelve data bits, most significant first.
PAGE 14
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com TYPICAL APPLICATION CIRCUIT A typical application of the ADC is shown in Figure 19. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC.
PAGE 15
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 MODES OF OPERATION The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought low again.
PAGE 16
ADC121S101 SNAS304F – JANUARY 2006 – REVISED MAY 2013 www.ti.com If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully powered-up after 16 SCLK cycles.
PAGE 17
ADC121S101 www.ti.com SNAS304F – JANUARY 2006 – REVISED MAY 2013 REVISION HISTORY Changes from Revision E (May 2013) to Revision F • Page Changed layout of National Data Sheet to TI format. .........................................................................................................
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC121S101CIMF/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADC121S101CISD/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 NGF 6 4500 330.0 12.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC121S101CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 WSON NGF 6 1000 210.0 185.0 35.0 WSON NGF 6 4500 367.0 367.0 35.
PAGE 22
PAGE 23
MECHANICAL DATA NGF0006A www.ti.
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.