Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply VSSOP 8

GND

CS SCLK

DOUT

DIN

IN1

ADC122S051

IN2

ADC122S051

www.ti.com

SNAS257E –NOVEMBER 2004–REVISED MARCH 2013

ADC122S051/ADC122S051Q 2 Channel, 200 ksps to 500 ksps 12-Bit A/D Converter

Check for Samples: ADC122S051

FEATURES

DESCRIPTION

The ADC122S051/ADC122S051Q is a low-power,

• Specified Over a Range of Sample Rates.

two-channel CMOS 12-bit analog-to-digital converter

• Two Input Channels

with a high-speed serial interface. Unlike the

• Variable Power Management

conventional practice of specifying performance at a

single sample rate only, the

• Single Power Supply with 2.7V - 5.25V Range

ADC122S051/ADC122S051Q is fully specified over a

• Tested per AEC-Q100 and Qualified for

sample rate range of 200 ksps to 500 ksps. The

Automotive Applications

converter is based on a successive-approximation

• Meets AEC-Q100-011 C2 CDM Classification

circuit. It can be configured to accept one or two input

signals at inputs IN1 and IN2.

APPLICATIONS

• Portable Systems The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

• Remote Data Acquisition

QSPI™, MICROWIRE, and many common DSP

• Instrumentation and Control Systems

serial interfaces.

The ADC122S051/ADC122S051Q operates with a

KEY SPECIFICATIONS

single supply that can range from +2.7V to +5.25V.

• DNL: +0.7 / −0.4 LSB (typ)

Normal power consumption using a +3V or +5V

supply is 3.0 mW and 10 mW, respectively. The

• INL: ± 0.50 LSB (typ)

power-down feature reduces the power consumption

• SNR: 72.5 dB (typ)

to just 0.14 µW using a +3V supply, or 0.32 µW using

• Power Consumption:

a +5V supply.

– 3V Supply: 3.0 mW (typ)

The ADC122S051/ADC122S051Q is packaged in an

– 5V Supply: 10 mW (typ)

8-lead VSSOP package. Operation over the industrial

temperature range of −40°C to +85°C is specified.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 ADC122S051/ADC122S051Q 2 Channel, 200 ksps to 500 ksps 12-Bit A/D Converter Check for Samples: ADC122S051 FEATURES DESCRIPTION • • • • • APPLICATIONS The ADC122S051/ADC122S051Q is a low-power, two-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Block Diagram IN1 MUX T/H IN2 12-BIT SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 7 DOUT Digital data output.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to VA +0.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC122S051/ADC122S051Q Converter Electrical Characteristics (1) (2) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 35 pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 ADC122S051/ADC122S051Q Converter Electrical Characteristics(1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 35 pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC122S051/ADC122S051Q Timing Specifications (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Limits Typical VA = +3.0V −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +14.5 VA = +5.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 IOL 200 PA To Output Pin 1.6V CL 35 pF IOH 200 PA Figure 2. Timing Test Circuit CS tACQ tCONVERT tCH SCLK 1 2 3 4 tEN DOUT Z3 tSU DIN 5 6 Z2 Z1 7 8 16 tACC tCL Z0 DB11 DB10 tDIS DB9 DB8 DB1 DB0 tH DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 3. Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 4.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as THD = 20 ‡ log10 A f 22 + + A f 62 A f 12 (2) where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL - VA = 3.0V INL - VA = 3.0V Figure 5. Figure 6. DNL - VA = 5.0V INL - VA = 5.0V Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 11. Figure 12. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 13. Figure 14. DNL vs. Temperature INL vs. Temperature Figure 15. Figure 16.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. Supply THD vs. Supply Figure 17. Figure 18. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 19. Figure 20. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 21. Figure 22.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Input Frequency THD vs. Input Frequency Figure 23. Figure 24. SNR vs. Temperature THD vs. Temperature Figure 25. Figure 26. SFDR vs. Supply SINAD vs. Supply Figure 27. Figure 28.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 29. Figure 30. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 31. Figure 32. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 33. Figure 34.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SFDR vs. Temperature SINAD vs. Temperature Figure 35. Figure 36. ENOB vs. Supply ENOB vs. Clock Frequency Figure 37. Figure 38. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 39. Figure 40.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 16 ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 41. Figure 42. Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps Figure 43. Figure 44. Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput Figure 45. Figure 46.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 APPLICATIONS INFORMATION ADC122S051/ADC122S051Q OPERATION For the rest of this document, the ADC122S051/ADC122S051Q will be referred to as the ADC122S051. The ADC122S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC122S051 in both track and hold modes are shown in Figure 47 and Figure 48, respectively.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 111...111 111...000 | | ADC CODE 111...110 1LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V +VA - 1.5LSB 0.5LSB ANALOG INPUT Figure 49. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC122S051 is shown in Figure 50. Power is provided, in this example, by the TI LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages.
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ADC122S051 SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com VA D1 R1 C2 30 pF VIN C1 3 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 51. Equivalent Input Circuit DIGITAL INPUTS AND OUTPUTS The ADC122S051's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latch-up risk.
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ADC122S051 www.ti.com SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC122S051CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC122S051CIMMX/NOP VSSOP B DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC122S051QIMM/NOP B VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC122S051CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.0 VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.
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