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CS SCLK

DOUT

DIN

IN1

GND

ADC122S101

IN2

ADC122S101

www.ti.com

SNAS286D –MARCH 2005–REVISED MARCH 2013

ADC122S101 2 Channel, 500 ksps to 1 Msps 12-Bit A/D Converter

Check for Samples: ADC122S101

FEATURES

DESCRIPTION

The ADC122S101 is a low-power, two-channel

• Specified Over a Range of Sample Rates

CMOS 12-bit analog-to-digital converter with a high-

• Two Input Channels

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC122S101 is fully specified over a

• Single power supply with 2.7V - 5.25V range

sample rate range of 500 ksps to 1 Msps. The

converter is based on a successive-approximation

APPLICATIONS

• Portable Systems

circuit. It can be configured to accept one or two input

signals at inputs IN1 and IN2.

• Remote Data Acquisition

• Instrumentation and Control Systems

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

KEY SPECIFICATIONS

serial interfaces.

• DNL: +0.9 / −0.6 LSB (typ)

The ADC122S101 operates with a single supply that

• INL: ±0.64 LSB (typ)

can range from +2.7V to +5.25V. Normal power

• SNR: 72.4 dB (typ)

consumption using a +3V or +5V supply is 4.3 mW

• Power Consumption

and 13.1 mW, respectively. The power-down feature

reduces the power consumption to just 0.14 µW using

– 3V Supply: 4.3 mW (typ)

a +3V supply, or 0.32 µW using a +5V supply.

– 5V Supply: 13.1 mW (typ)

The ADC122S101 is available in an 8-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C is ensured.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. PIN-COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Figure 1. 8-Lead VSSOP

See DGK Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 ADC122S101 2 Channel, 500 ksps to 1 Msps 12-Bit A/D Converter Check for Samples: ADC122S101 FEATURES DESCRIPTION • • • • The ADC122S101 is a low-power, two-channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC122S101 is fully specified over a sample rate range of 500 ksps to 1 Msps.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com Block Diagram IN1 MUX T/H IN2 12-BIT SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT Figure 2. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 5 ,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA. 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 7 DOUT Digital data output.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA Voltage on Any Pin to GND −0.3V to VA +0.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com ADC122S101 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7 V to 5.25 V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps, CL = 35 pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) 12 Bits +0.64 +1.6 LSB (max) −0.64 −1.2 LSB (min) +0.9 +1.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 ADC122S101 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7 V to 5.25 V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps, CL = 35 pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com ADC122S101 Timing Specifications (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol tCL Parameter SCLK Low Pulse Width Output Falling tDIS Typical Limits (1) Units 0.5 x tSCLK 0.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 CS tACQ tCONVERT tCH SCLK 1 2 3 4 6 DOUT Z3 tSU Z2 Z1 7 8 16 tACC tCL tEN DIN 5 Z0 DB11 DB10 tDIS DB9 DB8 DB1 DB0 tH DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 5. ADC122S101 Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 6. SCLK and CS Timing Parameters Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components that are present at the output and are not present at the input and result from two sinusoidal frequencies being applied to the ADC input at the same time.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V Figure 7. Figure 8. DNL - VA = 5.0V INL - VA = 5.0V Figure 9. Figure 10. DNL vs. Supply INL vs. Supply Figure 11. Figure 12.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. 10 DNL vs. Clock Frequency INL vs. Clock Frequency Figure 13. Figure 14. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 15. Figure 16. DNL vs. Temperature INL vs. Temperature Figure 17. Figure 18.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. SNR vs. Supply THD vs. Supply Figure 19. Figure 20. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 21. Figure 22. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 23. Figure 24.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. 12 SNR vs. Input Frequency THD vs. Input Frequency Figure 25. Figure 26. SNR vs. Temperature THD vs. Temperature Figure 27. Figure 28. SFDR vs. Supply SINAD vs. Supply Figure 29. Figure 30.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 31. Figure 32. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 33. Figure 34. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 35. Figure 36.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. 14 SFDR vs. Temperature SINAD vs. Temperature Figure 37. Figure 38. ENOB vs. Supply ENOB vs. Clock Frequency Figure 39. Figure 40. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 41. Figure 42.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. ENOB vs. Temperature Spectral Response - 3V, 500 ksps Figure 43. Figure 44. Spectral Response - 5V, 500 ksps Spectral Response - 3V, 1 Msps Figure 45. Figure 46. Spectral Response - 5V, 1 Msps Power Consumption vs. Throughput Figure 47. Figure 48.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC122S101 OPERATION The ADC122S101 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC122S101 in both track and hold modes are shown in Figure 49 and Figure 50, respectively.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com ADC122S101 TRANSFER FUNCTION The output format of the ADC122S101 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC122S101 is VA/4096. The ideal transfer characteristic is shown in Figure 51. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. Figure 51.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 The capacitor C1 in Figure 53 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC122S101 sampling capacitor and is typically 30 pF. The ADC122S101 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.
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ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 35 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance.
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ADC122S101 www.ti.com SNAS286D – MARCH 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC122S101CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC122S101CIMMX/NOP VSSOP B DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC122S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.
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