Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 10

SCLK

OUT

CHA -

CHA+

ADC122S625

REF

CHB -

CHB+ GND

ADC122S625

www.ti.com

SNAS451A –FEBRUARY 2008–REVISED MARCH 2013

ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter

Check for Samples: ADC122S625

FEATURES

DESCRIPTION

The ADC122S625 is a dual 12-bit, 50 kSPS to 200

• True Simultaneous Sampling Differential

kSPS simultaneous sampling Analog-to-Digital (A/D)

Inputs

converter. The analog inputs on both channels are

• Specified Performance from 50 kSPS to 200

sampled simultaneously to preserve their relative

kSPS

phase information to each other. The converter is

based on a successive-approximation register

• External Reference

architecture where the differential nature of the

• Wide Input Common-Mode Voltage Range

analog inputs is maintained from the internal track-

• Single High-Speed Serial Data Output

and-hold circuits throughout the A/D converter to

• Operating Temperature Range of −40°C to

provide excellent common-mode signal rejection. The

ADC122S625 features an external reference that can

+105°C

be varied from 1.0V to V

• SPI™/ QSPI™/MICROWIRE/DSP Compatible

Serial Interface

The ADC122S625's serial data output is binary 2's

complement and is compatible with several

standards, such as SPI™, QSPI™, MICROWIRE™,

APPLICATIONS

and many common DSP serial interfaces. The serial

• Motor Control

clock (SCLK) and chip select bar (CS) are shared by

• Power Meters/Monitors

both channels.

• Multi-Axis Positioning Systems

Operating from a single 5V analog supply and a

• Instrumentation and Control Systems

reference voltage of 2.5V, the total power

consumption while operating at 200 kSPS is typically

• Data Acquisition Systems

8.6 mW. With the ADC122S625 operating in power-

• Medical Instruments

down mode, the power consumption reduces to 2.6

• Direct Sensor Interface

µW. The differential input, low power consumption,

and small size make the ADC122S625 ideal for direct

connection to sensors in motor control applications.

KEY SPECIFICATIONS

• Conversion Rate: 50 kSPS to 200 kSPS Operation is specified over the industrial temperature

range of −40°C to +105°C and clock rates of 1.6 MHz

• INL: ±1 LSB (max)

to 6.4 MHz. The ADC122S625 is available in a 10-

• DNL: ±0.95 LSB (max)

lead VSSOP package.

• SNR: 71 dBc (min)

Connection Diagram

• THD: -72 dBc (min)

• ENOB: 11.25 bits (min)

• Power Consumption at 200 kSPS

– Converting, V

= 5V, V

REF

= 2.5V: 8.6 mW

(typ)

– Power-Down, V

= 5V, V

REF

= 2.5V: 2.6 µW

(typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Incorporated.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter Check for Samples: ADC122S625 FEATURES DESCRIPTION • The ADC122S625 is a dual 12-bit, 50 kSPS to 200 kSPS simultaneous sampling Analog-to-Digital (A/D) converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other.
PAGE 2
ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Block Diagram SAR CHA+ S/H CHA- CHARGE REDISTRIBUTION DAC COMPARATOR SERIAL INTERFACE SAR VREF CHBS/H CHB+ CHARGE REDISTRIBUTION DAC COMPARATOR PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol 1 VREF Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.
PAGE 3
ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA Voltage on Any Pin to GND −0.3V to (VA +0.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com ADC122S625 Converter Electrical Characteristics (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 to 6.4 MHz, fIN = 20 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 ADC122S625 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 to 6.4 MHz, fIN = 20 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units POWER SUPPLY CHARACTERISTICS 4.5 V (min) 5.5 V (max) 1.7 2.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Timing Diagrams tACQ tCONV CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DOUT DB11 DB10 DB9 4 Leading Zeroes DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Channel A Data tPower Down CS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCLK DOUT DB11 DB10 DB9 4 Leading Zeroes DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Channel B Data Figure 1.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 SCLK 1 2 tCSSU CS Figure 5. Valid CS Assertion Times CS VIH 90% 90% DOUT 10% tDIS 90% DOUT 10% 10% Figure 6. Voltage Waveform for tDIS Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the ADC122S625, VA is changed from 4.5V to 5.5V.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. DNL - 200 kSPS INL - 200 kSPS Figure 7. Figure 8. DNL vs. VA INL vs. VA Figure 9. Figure 10. DNL vs. VREF INL vs. VREF Figure 11. Figure 12.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. 10 DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY Figure 13. Figure 14. DNL vs. TEMPERATURE INL vs. TEMPERATURE Figure 15. Figure 16. SINAD vs. VA THD vs. VA Figure 17. Figure 18.
PAGE 11
ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. SINAD vs. VREF THD vs. VREF Figure 19. Figure 20. SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 21. Figure 22. SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 23. Figure 24.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. 12 SINAD vs. TEMPERATURE THD vs. TEMPERATURE Figure 25. Figure 26. VA CURRENT vs. VA VA CURRENT vs. SCLK FREQ Figure 27. Figure 28. VA CURRENT vs. TEMPERATURE VREF CURRENT vs. SCLK FREQ Figure 29. Figure 30.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. VREF CURRENT vs. TEMP CMRR vs. CM RIPPLE FREQ Figure 31. Figure 32. SPECTRAL RESPONSE - 200 kSPS Figure 33.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC122S625 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter.
PAGE 15
ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 ANALOG SIGNAL INPUTS The ADC122S625 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input.
PAGE 16
ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC122S625. The ranges of VCM for differential and single-ended operation are depicted in Figure 36 and Figure 37. Equations for calculating the minimum and maximum common mode voltages for differential and single-ended operation are shown in Table 1.
PAGE 17
ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 During the first three cycles of SCLK, the ADC122S625 is in acquisition mode (tACQ), tracking the input voltage on both Channel A and Channel B. For the next twelve SCLK cycles (tCONV), the conversion of Channel A and Channel B is accomplished simultaneously and data is presented on DOUT, one bit at a time.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Table 2. Ideal Output Code vs. Input Voltage Analog Input (+IN) − (−IN) 2's Complement Binary Output 2's Comp. Hex Code 2's Comp. Dec Code VREF − 1.5 LSB 0111 1111 1111 7FF 2047 + 0.5 LSB 0000 0000 0001 001 1 − 0.5 LSB 0000 0000 0000 000 0 0V − 1.5 LSB 1111 1111 1111 FFF −1 −VREF + 0.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 Analog Power Supply Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC122S625 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the ADC122S625 supply, with the 0.
PAGE 20
ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com APPLICATION CIRCUITS The following figures are examples of the ADC122S625 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. Data Acquisition Figure 38 shows a basic low cost, low power data acquisition circuit. The analog supply pin is powered by the system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt reference.
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ADC122S625 www.ti.com SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 Bridge Sensor Application Figure 40 shows an example of interfacing the ADC122S625 to a pair of bridge sensors. The application assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists of a pair of opamps from the LMP7704.
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ADC122S625 SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Original (March 2013) to Revision A • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC122S625CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC122S625CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC122S625CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
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