Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply TSSOP 16

8 9

CS SCLK

DOUT

AGND DIN

IN0 V

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC128S052

www.ti.com

SNAS333D –AUGUST 2005–REVISED MARCH 2013

ADC128S052/ADC128S052Q 8-Channel, 200 kSPS to 500 kSPS, 12-Bit A/D Converter

Check for Samples: ADC128S052

FEATURES

DESCRIPTION

The ADC128S052 is a low-power, eight-channel

• ADC128S052Q is AECQ100 Qualified to

CMOS 12-bit analog-to-digital converter specified for

Grade1 and is Manufactured on an Automotive

conversion throughput rates of 200 kSPS to 500

Grade Flow

kSPS. The converter is based on a successive-

• Eight Input Channels

approximation register architecture with an internal

track-and-hold circuit. It can be configured to accept

• Variable Power Management

up to eight input signals at inputs IN0 through IN7.

• Independent Analog and Digital Supplies

The output serial data is straight binary and is

• SPI/QSPI/MICROWIRE/DSP Compatible

compatible with several standards, such as SPI,

• Packaged in 16-Lead TSSOP

QSPI, MICROWIRE, and many common DSP serial

interfaces.

APPLICATIONS

The ADC128S052 may be operated with independent

• Automotive Navigation

analog and digital supplies. The analog supply (V

)

• Portable Systems

can range from +2.7V to +5.25V, and the digital

supply (V

) can range from +2.7V to V

. Normal

• Medical Instruments

power consumption using a +3V or +5V supply is 1.6

• Mobile Communications

mW and 8.7 mW, respectively. The power-down

• Instrumentation and Control Systems

feature reduces the power consumption to 0.06 µW

using a +3V supply and 0.25 µW using a +5V supply.

KEY SPECIFICATIONS

The ADC128S052/ADC128S052Q is packaged in a

• Conversion Rate 200 kSPS to 500 kSPS

16-lead TSSOP package. The ADC128S052 is

guaranteed over the extended industrial

• DNL (VA = VD = 5.0 V) +1.3 / −0.9 LSB (max)

temperature range of −40°C to +105°C while the

• INL (VA = VD = 5.0 V) ±1.0 LSB (max)

ADC128S052Q is guaranteed to an AECQ100

• Power Consumption

Grade 1 automotive temperature range of −40°C

to +125°C.

– 3V Supply 1.6 mW (typ)

– 5V Supply 8.7 mW (typ)

Connection Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 ADC128S052/ADC128S052Q 8-Channel, 200 kSPS to 500 kSPS, 12-Bit A/D Converter Check for Samples: ADC128S052 FEATURES DESCRIPTION • The ADC128S052 is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of 200 kSPS to 500 kSPS. The converter is based on a successiveapproximation register architecture with an internal track-and-hold circuit.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Block Diagram IN0 . . . MUX T/H 12-BIT SUCCESSIVE APPROXIMATION ADC VA AGND AGND IN7 VD SCLK ADC128S052 CONTROL LOGIC CS DIN DOUT DGND PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF. DIGITAL I/O 16 SCLK Digital clock input. The guaranteed performance range of frequencies for this input is 3.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to VA + 0.3V, max 6.5V −0.3V to VA +0.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com ADC128S052 Converter Electrical Characteristics (1) The following specifications apply for AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 ADC128S052 Converter Electrical Characteristics (1) (continued) The following specifications apply for AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com ADC128S052 Converter Electrical Characteristics (1) (continued) The following specifications apply for AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions fS Sample Rate Continuous Mode VA = VD = +2.7V to +5.25V tCONVERT Conversion (Hold) Time VA = VD = +2.7V to +5.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 CS tCONVERT tACQ tCH SCLK 1 2 3 4 5 6 7 DOUT 16 tDACC tCL tEN 8 DB11 FOUR ZEROS DB10 tDHLD DB9 DB8 tDIS DB1 DB0 tDH tDS DIN DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 2. ADC128S052 Serial Timing Diagram SCLK tCSS CS tCSH CS Figure 3. SCLK and CS Timing Parameters Specification Definitions ACQUISITION TIME is the time required for the ADC to acquire the input voltage.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition).
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL DNL Figure 4. Figure 5. INL INL Figure 6. Figure 7. DNL vs. Supply INL vs. Supply Figure 8. Figure 9.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 SNR vs. Supply THD vs. Supply Figure 10. Figure 11. ENOB vs. Supply DNL vs. VD with VA = 5.0 V Figure 12. Figure 13. INL vs. VD with VA = 5.0 V DNL vs. SCLK Duty Cycle Figure 14. Figure 15.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle Figure 16. Figure 17. THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle Figure 18. Figure 19. DNL vs. SCLK INL vs. SCLK Figure 20. Figure 21.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. SCLK THD vs. SCLK Figure 22. Figure 23. ENOB vs. SCLK DNL vs. Temperature Figure 24. Figure 25. INL vs. Temperature SNR vs. Temperature Figure 26. Figure 27.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. THD vs. Temperature ENOB vs. Temperature Figure 28. Figure 29. SNR vs. Input Frequency THD vs. Input Frequency Figure 30. Figure 31. ENOB vs. Input Frequency Power Consumption vs. SCLK Figure 32. Figure 33.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC128S052 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. ADC128S052 OPERATION Simplified schematics of the ADC128S052 in both track and hold operation are shown in Figure 34 and Figure 35 respectively.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com 111...111 111...000 | | ADC CODE 111...110 1LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V 0.5LSB ANALOG INPUT +VA - 1.5LSB Figure 36. Ideal Transfer Characteristic ANALOG INPUTS An equivalent circuit for one of the ADC128S052's input channels is shown in Figure 37. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 Applications Information TYPICAL APPLICATION CIRCUIT A typical application is shown in Figure 38. The split analog and digital supply pins are both powered in this example by the LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC128S052. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors.
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ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com PC = tS tN x PN + x PS tN + t S tN + t S Figure 39. Power Consumption Equation Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC.
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ADC128S052 www.ti.com SNAS333D – AUGUST 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC128S052CIMTX Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 ADC128S052CIMTX/NOP B TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 ADC128S052QCMTX/NO PB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC128S052CIMTX TSSOP PW 16 2500 367.0 367.0 35.0 ADC128S052CIMTX/NOP B TSSOP PW 16 2500 367.0 367.0 35.0 ADC128S052QCMTX/NOP B TSSOP PW 16 2500 367.0 367.0 35.
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